文件名称:dds_8bit
介绍说明－－下载内容均来自于网络，请自行研究使用
rom地址宽度8位，256个正弦波数据。频率控制字可以步进，具有清零功能。-rom address the width of 8, 256 sine wave data. Frequency control word can step has cleared function.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
dds_8bit
........\DDS_2
........\.....\ADDER30B.vhd
........\.....\ADDER8B.vhd
........\.....\COUNT_KEY.vhd
........\.....\db
........\.....\..\add_sub_aah.tdf
........\.....\..\add_sub_fnh.tdf
........\.....\..\add_sub_gah.tdf
........\.....\..\add_sub_jch.tdf
........\.....\..\add_sub_rjh.tdf
........\.....\..\altsyncram_qiv.tdf
........\.....\..\DDS_VHDL.analyze_file.qmsg
........\.....\..\DDS_VHDL.asm.qmsg
........\.....\..\DDS_VHDL.cbx.xml
........\.....\..\DDS_VHDL.cmp.cdb
........\.....\..\DDS_VHDL.cmp.hdb
........\.....\..\DDS_VHDL.cmp.kpt
........\.....\..\DDS_VHDL.cmp.logdb
........\.....\..\DDS_VHDL.cmp.rdb
........\.....\..\DDS_VHDL.cmp.tdb
........\.....\..\DDS_VHDL.cmp0.ddb
........\.....\..\DDS_VHDL.dbp
........\.....\..\DDS_VHDL.db_info
........\.....\..\DDS_VHDL.eco.cdb
........\.....\..\DDS_VHDL.fit.qmsg
........\.....\..\DDS_VHDL.hier_info
........\.....\..\DDS_VHDL.hif
........\.....\..\DDS_VHDL.map.cdb
........\.....\..\DDS_VHDL.map.hdb
........\.....\..\DDS_VHDL.map.logdb
........\.....\..\DDS_VHDL.map.qmsg
........\.....\..\DDS_VHDL.pre_map.cdb
........\.....\..\DDS_VHDL.pre_map.hdb
........\.....\..\DDS_VHDL.psp
........\.....\..\DDS_VHDL.rtlv.hdb
........\.....\..\DDS_VHDL.rtlv_sg.cdb
........\.....\..\DDS_VHDL.rtlv_sg_swap.cdb
........\.....\..\DDS_VHDL.sgdiff.cdb
........\.....\..\DDS_VHDL.sgdiff.hdb
........\.....\..\DDS_VHDL.sld_design_entry.sci
........\.....\..\DDS_VHDL.sld_design_entry_dsc.sci
........\.....\..\DDS_VHDL.syn_hier_info
........\.....\..\DDS_VHDL.tan.qmsg
........\.....\DDS_VHDL.asm.rpt
........\.....\DDS_VHDL.cdf
........\.....\DDS_VHDL.done
........\.....\DDS_VHDL.dpf
........\.....\DDS_VHDL.fit.rpt
........\.....\DDS_VHDL.fit.smsg
........\.....\DDS_VHDL.fit.summary
........\.....\DDS_VHDL.flow.rpt
........\.....\DDS_VHDL.map.rpt
........\.....\DDS_VHDL.map.summary
........\.....\DDS_VHDL.pin
........\.....\DDS_VHDL.pof
........\.....\DDS_VHDL.qpf
........\.....\DDS_VHDL.qsf
........\.....\DDS_VHDL.qws
........\.....\DDS_VHDL.sof
........\.....\DDS_VHDL.tan.rpt
........\.....\DDS_VHDL.tan.summary
........\.....\DDS_VHDL.vhd
........\.....\REG30B.VHDL
........\.....\REG8B.vhd
........\.....\ROM.MIF
........\.....\SIN_ROM.bsf
........\.....\SIN_ROM.cmp
........\.....\SIN_ROM.vhd
........\DDS_2数据记录.txt
........\DDS_2
........\.....\ADDER30B.vhd
........\.....\ADDER8B.vhd
........\.....\COUNT_KEY.vhd
........\.....\db
........\.....\..\add_sub_aah.tdf
........\.....\..\add_sub_fnh.tdf
........\.....\..\add_sub_gah.tdf
........\.....\..\add_sub_jch.tdf
........\.....\..\add_sub_rjh.tdf
........\.....\..\altsyncram_qiv.tdf
........\.....\..\DDS_VHDL.analyze_file.qmsg
........\.....\..\DDS_VHDL.asm.qmsg
........\.....\..\DDS_VHDL.cbx.xml
........\.....\..\DDS_VHDL.cmp.cdb
........\.....\..\DDS_VHDL.cmp.hdb
........\.....\..\DDS_VHDL.cmp.kpt
........\.....\..\DDS_VHDL.cmp.logdb
........\.....\..\DDS_VHDL.cmp.rdb
........\.....\..\DDS_VHDL.cmp.tdb
........\.....\..\DDS_VHDL.cmp0.ddb
........\.....\..\DDS_VHDL.dbp
........\.....\..\DDS_VHDL.db_info
........\.....\..\DDS_VHDL.eco.cdb
........\.....\..\DDS_VHDL.fit.qmsg
........\.....\..\DDS_VHDL.hier_info
........\.....\..\DDS_VHDL.hif
........\.....\..\DDS_VHDL.map.cdb
........\.....\..\DDS_VHDL.map.hdb
........\.....\..\DDS_VHDL.map.logdb
........\.....\..\DDS_VHDL.map.qmsg
........\.....\..\DDS_VHDL.pre_map.cdb
........\.....\..\DDS_VHDL.pre_map.hdb
........\.....\..\DDS_VHDL.psp
........\.....\..\DDS_VHDL.rtlv.hdb
........\.....\..\DDS_VHDL.rtlv_sg.cdb
........\.....\..\DDS_VHDL.rtlv_sg_swap.cdb
........\.....\..\DDS_VHDL.sgdiff.cdb
........\.....\..\DDS_VHDL.sgdiff.hdb
........\.....\..\DDS_VHDL.sld_design_entry.sci
........\.....\..\DDS_VHDL.sld_design_entry_dsc.sci
........\.....\..\DDS_VHDL.syn_hier_info
........\.....\..\DDS_VHDL.tan.qmsg
........\.....\DDS_VHDL.asm.rpt
........\.....\DDS_VHDL.cdf
........\.....\DDS_VHDL.done
........\.....\DDS_VHDL.dpf
........\.....\DDS_VHDL.fit.rpt
........\.....\DDS_VHDL.fit.smsg
........\.....\DDS_VHDL.fit.summary
........\.....\DDS_VHDL.flow.rpt
........\.....\DDS_VHDL.map.rpt
........\.....\DDS_VHDL.map.summary
........\.....\DDS_VHDL.pin
........\.....\DDS_VHDL.pof
........\.....\DDS_VHDL.qpf
........\.....\DDS_VHDL.qsf
........\.....\DDS_VHDL.qws
........\.....\DDS_VHDL.sof
........\.....\DDS_VHDL.tan.rpt
........\.....\DDS_VHDL.tan.summary
........\.....\DDS_VHDL.vhd
........\.....\REG30B.VHDL
........\.....\REG8B.vhd
........\.....\ROM.MIF
........\.....\SIN_ROM.bsf
........\.....\SIN_ROM.cmp
........\.....\SIN_ROM.vhd
........\DDS_2数据记录.txt