文件名称:ac97_verilog_sourcecode
介绍说明－－下载内容均来自于网络，请自行研究使用
AC97芯片的verilog实现，有兴趣可以研究下。verilog是一种硬件开发语言，语法与c类似。与VHDL并列为IC开发两大编程语言-AC97 chip Verilog realize, who are interested can study. Verilog is a hardware development language, grammar and c similar. IC with VHDL as a programming language to develop two
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(系统自动生成,下载前可以参看下载内容)
下载文件列表
ac97_ctrl
.........\bench
.........\.....\CVS
.........\.....\...\Entries
.........\.....\...\Entries.Log
.........\.....\...\Repository
.........\.....\...\Root
.........\.....\...\Template
.........\.....\verilog
.........\.....\.......\ac97_codec_sin.v
.........\.....\.......\ac97_codec_sout.v
.........\.....\.......\ac97_codec_top.v
.........\.....\.......\CVS
.........\.....\.......\...\Entries
.........\.....\.......\...\Repository
.........\.....\.......\...\Root
.........\.....\.......\...\Template
.........\.....\.......\tests.v
.........\.....\.......\test_bench_top.v
.........\.....\.......\wb_mast_model.v
.........\.....\.......\wb_model_defines.v
.........\CVS
.........\...\Entries
.........\...\Entries.Log
.........\...\Repository
.........\...\Root
.........\...\Template
.........\doc
.........\...\ac97_doc.pdf
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\...\Template
.........\...\README.txt
.........\...\STATUS.txt
.........\rtl
.........\...\CVS
.........\...\...\Entries
.........\...\...\Entries.Log
.........\...\...\Repository
.........\...\...\Root
.........\...\...\Template
.........\...\verilog
.........\...\.......\ac97_cra.v
.........\...\.......\ac97_defines.v
.........\...\.......\ac97_dma_if.v
.........\...\.......\ac97_dma_req.v
.........\...\.......\ac97_fifo_ctrl.v
.........\...\.......\ac97_int.v
.........\...\.......\ac97_in_fifo.v
.........\...\.......\ac97_out_fifo.v
.........\...\.......\ac97_prc.v
.........\...\.......\ac97_rf.v
.........\...\.......\ac97_rst.v
.........\...\.......\ac97_sin.v
.........\...\.......\ac97_soc.v
.........\...\.......\ac97_sout.v
.........\...\.......\ac97_top.v
.........\...\.......\ac97_wb_if.v
.........\...\.......\CVS
.........\...\.......\...\Entries
.........\...\.......\...\Repository
.........\...\.......\...\Root
.........\...\.......\...\Template
.........\sim
.........\...\CVS
.........\...\...\Entries
.........\...\...\Entries.Log
.........\...\...\Repository
.........\...\...\Root
.........\...\...\Template
.........\...\rtl_sim
.........\...\.......\bin
.........\...\.......\...\CVS
.........\...\.......\...\...\Entries
.........\...\.......\...\...\Repository
.........\...\.......\...\...\Root
.........\...\.......\...\...\Template
.........\...\.......\...\Makefile
.........\...\.......\CVS
.........\...\.......\...\Entries
.........\...\.......\...\Entries.Log
.........\...\.......\...\Repository
.........\...\.......\...\Root
.........\...\.......\...\Template
.........\...\.......\run
.........\...\.......\...\CVS
.........\...\.......\...\...\Entries
.........\...\.......\...\...\Repository
.........\...\.......\...\...\Root
.........\...\.......\...\...\Template
.........\...\.......\...\Makefile
.........\syn
.........\...\bin
.........\...\...\comp.dc
.........\...\...\CVS
.........\...\...\...\Entries
.........\...\...\...\Repository
.........\...\...\...\Root
.........\bench
.........\.....\CVS
.........\.....\...\Entries
.........\.....\...\Entries.Log
.........\.....\...\Repository
.........\.....\...\Root
.........\.....\...\Template
.........\.....\verilog
.........\.....\.......\ac97_codec_sin.v
.........\.....\.......\ac97_codec_sout.v
.........\.....\.......\ac97_codec_top.v
.........\.....\.......\CVS
.........\.....\.......\...\Entries
.........\.....\.......\...\Repository
.........\.....\.......\...\Root
.........\.....\.......\...\Template
.........\.....\.......\tests.v
.........\.....\.......\test_bench_top.v
.........\.....\.......\wb_mast_model.v
.........\.....\.......\wb_model_defines.v
.........\CVS
.........\...\Entries
.........\...\Entries.Log
.........\...\Repository
.........\...\Root
.........\...\Template
.........\doc
.........\...\ac97_doc.pdf
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\...\Template
.........\...\README.txt
.........\...\STATUS.txt
.........\rtl
.........\...\CVS
.........\...\...\Entries
.........\...\...\Entries.Log
.........\...\...\Repository
.........\...\...\Root
.........\...\...\Template
.........\...\verilog
.........\...\.......\ac97_cra.v
.........\...\.......\ac97_defines.v
.........\...\.......\ac97_dma_if.v
.........\...\.......\ac97_dma_req.v
.........\...\.......\ac97_fifo_ctrl.v
.........\...\.......\ac97_int.v
.........\...\.......\ac97_in_fifo.v
.........\...\.......\ac97_out_fifo.v
.........\...\.......\ac97_prc.v
.........\...\.......\ac97_rf.v
.........\...\.......\ac97_rst.v
.........\...\.......\ac97_sin.v
.........\...\.......\ac97_soc.v
.........\...\.......\ac97_sout.v
.........\...\.......\ac97_top.v
.........\...\.......\ac97_wb_if.v
.........\...\.......\CVS
.........\...\.......\...\Entries
.........\...\.......\...\Repository
.........\...\.......\...\Root
.........\...\.......\...\Template
.........\sim
.........\...\CVS
.........\...\...\Entries
.........\...\...\Entries.Log
.........\...\...\Repository
.........\...\...\Root
.........\...\...\Template
.........\...\rtl_sim
.........\...\.......\bin
.........\...\.......\...\CVS
.........\...\.......\...\...\Entries
.........\...\.......\...\...\Repository
.........\...\.......\...\...\Root
.........\...\.......\...\...\Template
.........\...\.......\...\Makefile
.........\...\.......\CVS
.........\...\.......\...\Entries
.........\...\.......\...\Entries.Log
.........\...\.......\...\Repository
.........\...\.......\...\Root
.........\...\.......\...\Template
.........\...\.......\run
.........\...\.......\...\CVS
.........\...\.......\...\...\Entries
.........\...\.......\...\...\Repository
.........\...\.......\...\...\Root
.........\...\.......\...\...\Template
.........\...\.......\...\Makefile
.........\syn
.........\...\bin
.........\...\...\comp.dc
.........\...\...\CVS
.........\...\...\...\Entries
.........\...\...\...\Repository
.........\...\...\...\Root