文件名称:LCD
- 所属分类：
- VHDL编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 1.05mb
- 下载次数：
- 0次
- 提 供 者：
- liang*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
基于FPGA的LCD1602驱动，verilog代码，已经调试成功-LCD1602-driven FPGA-based, verilog code debugging has been successful
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(系统自动生成,下载前可以参看下载内容)
下载文件列表
LCD实验
.......\Project
.......\.......\LCD_1602
.......\.......\........\component
.......\.......\........\constraint
.......\.......\........\..........\LCD_Top.pdc
.......\.......\........\coreconsole
.......\.......\........\designer
.......\.......\........\........\impl1
.......\.......\........\........\.....\designer.log
.......\.......\........\........\.....\LCD_Driver.ide_des
.......\.......\........\........\.....\LCD_Top.adb
.......\.......\........\........\.....\LCD_Top.dtf
.......\.......\........\........\.....\...........\verify.log
.......\.......\........\........\.....\LCD_Top.ide_des
.......\.......\........\........\.....\LCD_Top.pdb
.......\.......\........\........\.....\LCD_Top.pdb.depends
.......\.......\........\........\.....\LCD_Top.plk
.......\.......\........\........\.....\LCD_Top.tcl
.......\.......\........\........\.....\LCD_Top_ba.sdf
.......\.......\........\........\.....\LCD_Top_ba.v
.......\.......\........\........\.....\LCD_Top_fp
.......\.......\........\........\.....\..........\LCD_Top.log
.......\.......\........\........\.....\..........\LCD_Top.pro
.......\.......\........\........\.....\PLL_1M.ide_des
.......\.......\........\........\.....\simulation
.......\.......\........\hdl
.......\.......\........\...\Clock_Gen.v
.......\.......\........\...\LCD_Driver.v
.......\.......\........\...\LCD_Top.v
.......\.......\........\LCD_1602.prj
.......\.......\........\phy_synthesis
.......\.......\........\simulation
.......\.......\........\..........\meminit.dat
.......\.......\........\..........\modelsim.ini
.......\.......\........\..........\modelsim.ini.sav
.......\.......\........\smartgen
.......\.......\........\........\PLL_1M
.......\.......\........\........\......\PLL_1M.cxf
.......\.......\........\........\......\PLL_1M.gen
.......\.......\........\........\......\PLL_1M.log
.......\.......\........\........\......\PLL_1M.v
.......\.......\........\........\PLL_1M_work.ixf
.......\.......\........\........\smartgen.aws
.......\.......\........\stimulus
.......\.......\........\........\BtimErrors.log
.......\.......\........\........\LCD_Top.dsk
.......\.......\........\........\LCD_Top.hpj
.......\.......\........\........\waveperl.log
.......\.......\........\synthesis
.......\.......\........\.........\.recordref
.......\.......\........\.........\actgen
.......\.......\........\.........\component
.......\.......\........\.........\constraint
.......\.......\........\.........\coreconsole
.......\.......\........\.........\designer
.......\.......\........\.........\........\convert.log
.......\.......\........\.........\........\convert.tcl
.......\.......\........\.........\........\impl1
.......\.......\........\.........\........\.....\impl.prj_des
.......\.......\........\.........\........\.....\simulation
.......\.......\........\.........\........\impl2
.......\.......\........\.........\........\.....\simulation
.......\.......\........\.........\hdl
.......\.......\........\.........\LCD_Top.areasrr
.......\.......\........\.........\LCD_Top.edn
.......\.......\........\.........\LCD_Top.fse
.......\.......\........\.........\LCD_Top.htm
.......\.......\........\.........\LCD_Top.map
.......\.......\........\.........\LCD_Top.sap
.......\.......\........\.........\LCD_Top.sdf
.......\.......\........\.........\LCD_Top.srd
.......\.......\........\.........\LCD_Top.srm
.......\.......\........\.........\LCD_Top.srr
.......\.......\........\.........\LCD_Top.srs
.......\.......\........\.........\LCD_Top.tlg
.......\.......\........\.........\LCD_Top_sdc.sdc
.......\.......\........\.........\LCD_Top_syn.prj
.......\.......\........\.........\LCD_Top_syn.prj.convert.sav
.......\.......\........\.........\phy_synthesis
.......\.......\........\.........\simulation
.......\.......\........\.........\..........\modelsim.ini
.......\.......\........\.........\..........\modelsim.ini.sav
.......\.......\........\.........\smartgen
.......\.......\........\.........\stdout.log
.......\.......\........\.........\stimulus
.......\.......\........\.........\s
.......\Project
.......\.......\LCD_1602
.......\.......\........\component
.......\.......\........\constraint
.......\.......\........\..........\LCD_Top.pdc
.......\.......\........\coreconsole
.......\.......\........\designer
.......\.......\........\........\impl1
.......\.......\........\........\.....\designer.log
.......\.......\........\........\.....\LCD_Driver.ide_des
.......\.......\........\........\.....\LCD_Top.adb
.......\.......\........\........\.....\LCD_Top.dtf
.......\.......\........\........\.....\...........\verify.log
.......\.......\........\........\.....\LCD_Top.ide_des
.......\.......\........\........\.....\LCD_Top.pdb
.......\.......\........\........\.....\LCD_Top.pdb.depends
.......\.......\........\........\.....\LCD_Top.plk
.......\.......\........\........\.....\LCD_Top.tcl
.......\.......\........\........\.....\LCD_Top_ba.sdf
.......\.......\........\........\.....\LCD_Top_ba.v
.......\.......\........\........\.....\LCD_Top_fp
.......\.......\........\........\.....\..........\LCD_Top.log
.......\.......\........\........\.....\..........\LCD_Top.pro
.......\.......\........\........\.....\PLL_1M.ide_des
.......\.......\........\........\.....\simulation
.......\.......\........\hdl
.......\.......\........\...\Clock_Gen.v
.......\.......\........\...\LCD_Driver.v
.......\.......\........\...\LCD_Top.v
.......\.......\........\LCD_1602.prj
.......\.......\........\phy_synthesis
.......\.......\........\simulation
.......\.......\........\..........\meminit.dat
.......\.......\........\..........\modelsim.ini
.......\.......\........\..........\modelsim.ini.sav
.......\.......\........\smartgen
.......\.......\........\........\PLL_1M
.......\.......\........\........\......\PLL_1M.cxf
.......\.......\........\........\......\PLL_1M.gen
.......\.......\........\........\......\PLL_1M.log
.......\.......\........\........\......\PLL_1M.v
.......\.......\........\........\PLL_1M_work.ixf
.......\.......\........\........\smartgen.aws
.......\.......\........\stimulus
.......\.......\........\........\BtimErrors.log
.......\.......\........\........\LCD_Top.dsk
.......\.......\........\........\LCD_Top.hpj
.......\.......\........\........\waveperl.log
.......\.......\........\synthesis
.......\.......\........\.........\.recordref
.......\.......\........\.........\actgen
.......\.......\........\.........\component
.......\.......\........\.........\constraint
.......\.......\........\.........\coreconsole
.......\.......\........\.........\designer
.......\.......\........\.........\........\convert.log
.......\.......\........\.........\........\convert.tcl
.......\.......\........\.........\........\impl1
.......\.......\........\.........\........\.....\impl.prj_des
.......\.......\........\.........\........\.....\simulation
.......\.......\........\.........\........\impl2
.......\.......\........\.........\........\.....\simulation
.......\.......\........\.........\hdl
.......\.......\........\.........\LCD_Top.areasrr
.......\.......\........\.........\LCD_Top.edn
.......\.......\........\.........\LCD_Top.fse
.......\.......\........\.........\LCD_Top.htm
.......\.......\........\.........\LCD_Top.map
.......\.......\........\.........\LCD_Top.sap
.......\.......\........\.........\LCD_Top.sdf
.......\.......\........\.........\LCD_Top.srd
.......\.......\........\.........\LCD_Top.srm
.......\.......\........\.........\LCD_Top.srr
.......\.......\........\.........\LCD_Top.srs
.......\.......\........\.........\LCD_Top.tlg
.......\.......\........\.........\LCD_Top_sdc.sdc
.......\.......\........\.........\LCD_Top_syn.prj
.......\.......\........\.........\LCD_Top_syn.prj.convert.sav
.......\.......\........\.........\phy_synthesis
.......\.......\........\.........\simulation
.......\.......\........\.........\..........\modelsim.ini
.......\.......\........\.........\..........\modelsim.ini.sav
.......\.......\........\.........\smartgen
.......\.......\........\.........\stdout.log
.......\.......\........\.........\stimulus
.......\.......\........\.........\s