文件名称:DDS-in-Verilog

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 454kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • h***
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Verilog编写基于FPGA的DDS实现,内含源代码,希望对大家有所帮助。-DDS in Verilog FPGA-based implementation, including source code, we want to help.
相关搜索: verilog
DDS
DDS
verilog
code
DDS
verilog

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下载文件列表

Verilog编写基于FPGA的DDS实现\dds_using_FPGA\cos.mif

............................\..............\cos_rom.bsf

............................\..............\cos_rom.inc

............................\..............\cos_rom.tdf

............................\..............\db\add_sub_6fg.tdf

............................\..............\..\altsyncram_3u41.tdf

............................\..............\..\altsyncram_4pi2.tdf

............................\..............\..\altsyncram_90m1.tdf

............................\..............\..\altsyncram_9pi2.tdf

............................\..............\..\altsyncram_b431.tdf

............................\..............\..\altsyncram_ut41.tdf

............................\..............\..\altsyncram_vpl1.tdf

............................\..............\..\dds.analyze_file.qmsg

............................\..............\..\dds.asm.qmsg

............................\..............\..\dds.cbx.xml

............................\..............\..\dds.cmp.kpt

............................\..............\..\dds.cmp.rdb

............................\..............\..\dds.dbp

............................\..............\..\dds.db_info

............................\..............\..\dds.eco.cdb

............................\..............\..\dds.fit.qmsg

............................\..............\..\dds.hier_info

............................\..............\..\dds.hif

............................\..............\..\dds.map.hdb

............................\..............\..\dds.map.logdb

............................\..............\..\dds.map.qmsg

............................\..............\..\dds.pre_map.hdb

............................\..............\..\dds.psp

............................\..............\..\dds.rtlv.hdb

............................\..............\..\dds.rtlv_sg.cdb

............................\..............\..\dds.rtlv_sg_swap.cdb

............................\..............\..\dds.sgdiff.cdb

............................\..............\..\dds.sgdiff.hdb

............................\..............\..\dds.sld_design_entry.sci

............................\..............\..\dds.sld_design_entry_dsc.sci

............................\..............\..\dds.syn_hier_info

............................\..............\..\dds.tan.qmsg

............................\..............\..\decode_ogi.tdf

............................\..............\..\mux_ogc.tdf

............................\..............\dds.asm.rpt

............................\..............\dds.done

............................\..............\dds.fit.rpt

............................\..............\dds.fit.smsg

............................\..............\dds.fit.summary

............................\..............\dds.flow.rpt

............................\..............\dds.map.rpt

............................\..............\dds.map.summary

............................\..............\dds.pin

............................\..............\dds.qpf

............................\..............\dds.qsf

............................\..............\dds.qws

............................\..............\dds.tan.rpt

............................\..............\dds.tan.summary

............................\..............\dds_lut.bdf

............................\..............\dds_lut.bsf

............................\..............\dds_lut.v

............................\..............\mux4.bsf

............................\..............\mux4.inc

............................\..............\mux4.tdf

............................\..............\ram.bsf

............................\..............\ram.inc

............................\..............\ram.tdf

............................\..............\sin.mif

............................\..............\sin_rom.bsf

............................\..............\sin_rom.inc

............................\..............\sin_rom.tdf

............................\..............\square.bsf

............................\..............\square.inc

............................\..............\square.tdf

............................\........

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