文件名称:dpRam1
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Dual port ram design project developed in Xilinx using VHDL
(系统自动生成,下载前可以参看下载内容)
下载文件列表
dpRam1\.lso
......\ClockDivider.vhd
......\ClockDivider_summary.html
......\Clock_Divider_summary.html
......\D4to7.vhd
......\D4to7_Arch.vhd
......\device_usage_statistics.html
......\dpram.asy
......\dpram.edn
......\dpram.sym
......\dpram.v
......\dpram.veo
......\dpram.vhd
......\dpram.vho
......\dpram.xco
......\dpRam1.ise
......\dpRam1.ise_ISE_Backup
......\dpRam1.ntrc_log
......\dpram16x4.asy
......\dpram16x4.edn
......\dpram16x4.ngo
......\dpram16x4.sym
......\dpram16x4.v
......\dpram16x4.veo
......\dpram16x4.vhd
......\dpram16x4.vho
......\dpram16x4.xco
......\dpram16x4_flist.txt
......\dpram16x4_readme.txt
......\dpram_flist.txt
......\dpram_readme.txt
......\isim\temp\hdllib.ref
......\....\....\hdpdeps.ref
......\....\....\sub00\vhpl00.vho
......\....\....\.....\vhpl01.vho
......\....\....\.....\vhpl02.vho
......\....\....\.....\vhpl03.vho
......\....\....\.....\vhpl04.vho
......\....\....\.....\vhpl05.vho
......\....\....\.....\vhpl06.vho
......\....\....\.....\vhpl07.vho
......\....\....\.....\vhpl08.vho
......\....\....\.....\vhpl09.vho
......\....\work\clock_divider\behavioral.h
......\....\....\.............\mingw\behavioral.obj
......\....\....\d4to7\d4to7_arch.h
......\....\....\.....\mingw\d4to7_arch.obj
......\....\....\.pram16x4\dpram16x4.h
......\....\....\.........\mingw\dpram16x4.obj
......\....\....\glbl\glbl.h
......\....\....\....\mingw\glbl.obj
......\....\....\hdllib.ref
......\....\....\hdpdeps.ref
......\....\....\scan4digit\mingw\scan4digit_arch.obj
......\....\....\..........\scan4digit_arch.h
......\....\....\.ub00\vhpl00.vho
......\....\....\.....\vhpl01.vho
......\....\....\.....\vhpl02.vho
......\....\....\.....\vhpl03.vho
......\....\....\.....\vhpl04.vho
......\....\....\.....\vhpl05.vho
......\....\....\.....\vhpl06.vho
......\....\....\.....\vhpl07.vho
......\....\....\.....\vhpl08.vho
......\....\....\.....\vhpl09.vho
......\....\....\tb_toplevel_dualport_ram_xilinxcore\behav.h
......\....\....\...................................\mingw\behav.obj
......\....\....\...................................\xsimbehav.cpp
......\....\....\.oplevel_dualport_ram_xilinxcore\arch.h
......\....\....\................................\mingw\arch.obj
......\....\....\................................\xsimarch.cpp
......\....\....\vlg07\dpram16x4.bin
......\....\....\...2D\glbl.bin
......\....\xilinxcorelib_ver.auxlib\hdllib.ref
......\....\........................\_b_l_k_m_e_m_d_p___v6__3\mingw\_b_l_k_m_e_m_d_p___v6__3.obj
......\....\........................\........................\_b_l_k_m_e_m_d_p___v6__3.h
......\isim.cmd
......\isim.hdlsourcefiles
......\isim.log
......\.....tmp_save\_1
......\isimwavedata.xwv
......\pepExtractor.prj
......\Scan4Digit.vhd
......\tb_DpRam.vhd
......\tb_TopLevel_DualPort_Ram_XilinxCore_beh.prj
......\tb_TopLevel_DualPort_Ram_XilinxCore_isim_beh.exe
......\tb_TopLevel_DualPort_Ram_XilinxCore_stx.prj
......\tb_TopLevel_DualPort_Ram_XilinxCore_summary.html
......\.emplates\coregen.xml
......\toplevel.vhd
......\toplevel_dualport_ram_xilinxcore.bgn
......\toplevel_dualport_ram_xilinxcore.bit
......\TopLevel_DualPort_Ram_XilinxCore.bld
......\TopLevel_DualPort_Ram_XilinxCore.cmd_log
......\toplevel_dualport_ram_xilinxcore.drc
......\TopLevel_DualPort_Ram_XilinxCore.lfp
......\TopLevel_DualPort_Ram_XilinxCore.lso
......\TopLevel_DualPort_Ram_XilinxCore.ncd
......\TopLevel_DualPort_Ram_XilinxCore.ngc
......\TopLevel_DualPort_Ram_XilinxCore.ngd
......\ClockDivider.vhd
......\ClockDivider_summary.html
......\Clock_Divider_summary.html
......\D4to7.vhd
......\D4to7_Arch.vhd
......\device_usage_statistics.html
......\dpram.asy
......\dpram.edn
......\dpram.sym
......\dpram.v
......\dpram.veo
......\dpram.vhd
......\dpram.vho
......\dpram.xco
......\dpRam1.ise
......\dpRam1.ise_ISE_Backup
......\dpRam1.ntrc_log
......\dpram16x4.asy
......\dpram16x4.edn
......\dpram16x4.ngo
......\dpram16x4.sym
......\dpram16x4.v
......\dpram16x4.veo
......\dpram16x4.vhd
......\dpram16x4.vho
......\dpram16x4.xco
......\dpram16x4_flist.txt
......\dpram16x4_readme.txt
......\dpram_flist.txt
......\dpram_readme.txt
......\isim\temp\hdllib.ref
......\....\....\hdpdeps.ref
......\....\....\sub00\vhpl00.vho
......\....\....\.....\vhpl01.vho
......\....\....\.....\vhpl02.vho
......\....\....\.....\vhpl03.vho
......\....\....\.....\vhpl04.vho
......\....\....\.....\vhpl05.vho
......\....\....\.....\vhpl06.vho
......\....\....\.....\vhpl07.vho
......\....\....\.....\vhpl08.vho
......\....\....\.....\vhpl09.vho
......\....\work\clock_divider\behavioral.h
......\....\....\.............\mingw\behavioral.obj
......\....\....\d4to7\d4to7_arch.h
......\....\....\.....\mingw\d4to7_arch.obj
......\....\....\.pram16x4\dpram16x4.h
......\....\....\.........\mingw\dpram16x4.obj
......\....\....\glbl\glbl.h
......\....\....\....\mingw\glbl.obj
......\....\....\hdllib.ref
......\....\....\hdpdeps.ref
......\....\....\scan4digit\mingw\scan4digit_arch.obj
......\....\....\..........\scan4digit_arch.h
......\....\....\.ub00\vhpl00.vho
......\....\....\.....\vhpl01.vho
......\....\....\.....\vhpl02.vho
......\....\....\.....\vhpl03.vho
......\....\....\.....\vhpl04.vho
......\....\....\.....\vhpl05.vho
......\....\....\.....\vhpl06.vho
......\....\....\.....\vhpl07.vho
......\....\....\.....\vhpl08.vho
......\....\....\.....\vhpl09.vho
......\....\....\tb_toplevel_dualport_ram_xilinxcore\behav.h
......\....\....\...................................\mingw\behav.obj
......\....\....\...................................\xsimbehav.cpp
......\....\....\.oplevel_dualport_ram_xilinxcore\arch.h
......\....\....\................................\mingw\arch.obj
......\....\....\................................\xsimarch.cpp
......\....\....\vlg07\dpram16x4.bin
......\....\....\...2D\glbl.bin
......\....\xilinxcorelib_ver.auxlib\hdllib.ref
......\....\........................\_b_l_k_m_e_m_d_p___v6__3\mingw\_b_l_k_m_e_m_d_p___v6__3.obj
......\....\........................\........................\_b_l_k_m_e_m_d_p___v6__3.h
......\isim.cmd
......\isim.hdlsourcefiles
......\isim.log
......\.....tmp_save\_1
......\isimwavedata.xwv
......\pepExtractor.prj
......\Scan4Digit.vhd
......\tb_DpRam.vhd
......\tb_TopLevel_DualPort_Ram_XilinxCore_beh.prj
......\tb_TopLevel_DualPort_Ram_XilinxCore_isim_beh.exe
......\tb_TopLevel_DualPort_Ram_XilinxCore_stx.prj
......\tb_TopLevel_DualPort_Ram_XilinxCore_summary.html
......\.emplates\coregen.xml
......\toplevel.vhd
......\toplevel_dualport_ram_xilinxcore.bgn
......\toplevel_dualport_ram_xilinxcore.bit
......\TopLevel_DualPort_Ram_XilinxCore.bld
......\TopLevel_DualPort_Ram_XilinxCore.cmd_log
......\toplevel_dualport_ram_xilinxcore.drc
......\TopLevel_DualPort_Ram_XilinxCore.lfp
......\TopLevel_DualPort_Ram_XilinxCore.lso
......\TopLevel_DualPort_Ram_XilinxCore.ncd
......\TopLevel_DualPort_Ram_XilinxCore.ngc
......\TopLevel_DualPort_Ram_XilinxCore.ngd