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文件名称:cysteter

  • 所属分类：
  • VHDL编程
  • 资源属性：
  • [HTML]
  • 上传时间：
  • 2012-11-26
  • 文件大小：
  • 4.13mb
  • 下载次数：
  • 0次
  • 提 供 者：
  • t**
  • 相关连接：
  • 无
  • 下载说明：
  • 别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容均来自于网络，请自行研究使用

分频器，可以求出1--100000000Hz的所有的频率，基于xilinx公司的SPARTAN-3E板子。-Based on SPARTAN-3E of xilinx, using ISE and VHDL, i developed the cysteter.
相关搜索： 分频器
vhdl
分频
分频器
VHDL

(系统自动生成,下载前可以参看下载内容)

下载文件列表

cysteter

........\.lso

........\constrain.ucf

........\count10.vhd

........\count_circle.bgn

........\count_circle.bit

........\Count_circle.bld

........\Count_circle.cmd_log

........\count_circle.drc

........\Count_circle.fdo

........\Count_circle.lso

........\Count_circle.ncd

........\Count_circle.ngc

........\Count_circle.ngd

........\Count_circle.ngr

........\Count_circle.pad

........\Count_circle.par

........\Count_circle.pcf

........\Count_circle.prj

........\Count_circle.ptwx

........\Count_circle.stx

........\Count_circle.syr

........\Count_circle.twr

........\Count_circle.twx

........\Count_circle.udo

........\Count_circle.unroutes

........\Count_circle.ut

........\count_circle.vhd

........\Count_circle.xpi

........\Count_circle.xst

........\Count_circle_guide.ncd

........\Count_circle_map.map

........\Count_circle_map.mrp

........\Count_circle_map.ncd

........\Count_circle_map.ngm

........\Count_circle_map.xrpt

........\Count_circle_ngdbuild.xrpt

........\Count_circle_pad.csv

........\Count_circle_pad.txt

........\Count_circle_par.xrpt

........\Count_circle_prev_built.ngd

........\Count_circle_summary.html

........\Count_circle_summary.xml

........\Count_circle_usage.xml

........\Count_circle_vhdl.prj

........\Count_circle_wave.fdo

........\Count_circle_xst.xrpt

........\cysteter.gise

........\cysteter.ise

........\cysteter.ntrc_log

........\cysteter.xise

........\cysteter_xdb

........\............\cst.xbcd

........\............\tmp

........\............\...\ise

........\............\...\ise.lock

........\............\...\...\version

........\............\...\...\__OBJSTORE__

........\............\...\...\............\Autonym

........\............\...\...\............\common

........\............\...\...\............\ExpandedNetlistEngine

........\............\...\...\............\HierarchicalDesign

........\............\...\...\............\..................\HDProject

........\............\...\...\............\..................\.........\HDProject

........\............\...\...\............\..................\.........\HDProject_StrTbl

........\............\...\...\............\..................\__stored_object_table__

........\............\...\...\............\PnAutoRun

........\............\...\...\............\.........\Scripts

........\............\...\...\............\.........\.......\RunOnce_tcl

........\............\...\...\............\.........\.......\RunOnce_tcl_StrTbl

........\............\...\...\............\ProjectNavigator

........\............\...\...\............\ProjectNavigator11

........\............\...\...\............\ProjectNavigatorGui

........\............\...\...\............\...................\CViewSelector

........\............\...\...\............\...................\CViewSelector_StrTbl

........\............\...\...\............\...................\File-SynthesisOnly

........\............\...\...\............\...................\File-SynthesisOnly_StrTbl

........\............\...\...\............\...................\Library-SynthesisOnly

........\............\...\...\............\...................\Library-SynthesisOnly_StrTbl

........\............\...\...\............\...................\Process-BehavioralSim-

........\............\...\...\............\...................\Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE

........\............\...\...\............\...................\Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE_StrTbl

........\............\...\...\............\...................\Process-BehavioralSim-_StrTbl

........\............\...\...\............\...................\Process-SynthesisOnly-

........\............\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF

........\............\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF_StrTbl

........\............\...\...\............\...................\Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE

........\............\...\...\............\...................\Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE_StrTbl

........\............\...\...\............\..........

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