文件名称:PIPE_LINING_CPU_TEAM_24
介绍说明－－下载内容均来自于网络，请自行研究使用
采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。
能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）：
add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt
subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs
slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs
sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base)
lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs)
在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下：
ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段；
cpuctr.v用于产生CPU控制信号；
ALU.v用于对操作数进行相应指令的运算并输出结果；
DM.v数据存储器
IM.v指令存储器
datareg.v数据寄存器堆
extender.v位扩展
yiwei_32bits.v 实现32位四种移位方式的移位器
在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU.
To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end):
add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt
subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs
slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs
sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base)
lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs)
In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows:
ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph
cpuctr.v used to generate CPU control signal
ALU.v accordingly
能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）：
add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt
subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs
slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs
sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base)
lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs)
在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下：
ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段；
cpuctr.v用于产生CPU控制信号；
ALU.v用于对操作数进行相应指令的运算并输出结果；
DM.v数据存储器
IM.v指令存储器
datareg.v数据寄存器堆
extender.v位扩展
yiwei_32bits.v 实现32位四种移位方式的移位器
在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU.
To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end):
add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt
subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs
slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs
sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base)
lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs)
In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows:
ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph
cpuctr.v used to generate CPU control signal
ALU.v accordingly
(系统自动生成,下载前可以参看下载内容)
下载文件列表
PIPE_LINING_CPU_TEAM_24\ALU.v
.......................\ALU.v.bak
.......................\cpuctr.v
.......................\cpuctr.v.bak
.......................\datareg.v
.......................\datareg.v.bak
.......................\.b\PIPE_LINING_CPU_TEAM_24.asm.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.cbx.xml
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.bpm
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.ecobp
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.kpt
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.logdb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.rdb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.tdb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp0.ddb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp_merge.kpt
.......................\..\PIPE_LINING_CPU_TEAM_24.db_info
.......................\..\PIPE_LINING_CPU_TEAM_24.eco.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.eds_overflow
.......................\..\PIPE_LINING_CPU_TEAM_24.fit.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.hier_info
.......................\..\PIPE_LINING_CPU_TEAM_24.hif
.......................\..\PIPE_LINING_CPU_TEAM_24.lpc.html
.......................\..\PIPE_LINING_CPU_TEAM_24.lpc.rdb
.......................\..\PIPE_LINING_CPU_TEAM_24.lpc.txt
.......................\..\PIPE_LINING_CPU_TEAM_24.map.bpm
.......................\..\PIPE_LINING_CPU_TEAM_24.map.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.map.ecobp
.......................\..\PIPE_LINING_CPU_TEAM_24.map.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.map.kpt
.......................\..\PIPE_LINING_CPU_TEAM_24.map.logdb
.......................\..\PIPE_LINING_CPU_TEAM_24.map.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.map_bb.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.map_bb.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.map_bb.logdb
.......................\..\PIPE_LINING_CPU_TEAM_24.pre_map.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.pre_map.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.rpp.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.rtlv.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.rtlv_sg.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.rtlv_sg_swap.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.sgate.rvd
.......................\..\PIPE_LINING_CPU_TEAM_24.sgate_sm.rvd
.......................\..\PIPE_LINING_CPU_TEAM_24.sgdiff.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.sgdiff.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.sim.cvwf
.......................\..\PIPE_LINING_CPU_TEAM_24.sim.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.sim.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.sim.rdb
.......................\..\PIPE_LINING_CPU_TEAM_24.sld_design_entry.sci
.......................\..\PIPE_LINING_CPU_TEAM_24.sld_design_entry_dsc.sci
.......................\..\PIPE_LINING_CPU_TEAM_24.syn_hier_info
.......................\..\PIPE_LINING_CPU_TEAM_24.tan.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.tis_db_list.ddb
.......................\..\PIPE_LINING_CPU_TEAM_24.tmw_info
.......................\..\PIPE_LINING_CPU_TEAM_24_global_asgn_op.abo
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.asm.qmsg
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.fit.qmsg
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.map.qmsg
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.qmsg
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.sim.qmsg
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.tan.qmsg
.......................\..\wed.wsf
.......................\DM.v
.......................\DM.v.bak
.......................\exec.v
.......................\exec.v.bak
.......................\extender.v
.......................\extender.v.bak
.......................\ifetch.v
..............
.......................\ALU.v.bak
.......................\cpuctr.v
.......................\cpuctr.v.bak
.......................\datareg.v
.......................\datareg.v.bak
.......................\.b\PIPE_LINING_CPU_TEAM_24.asm.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.cbx.xml
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.bpm
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.ecobp
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.kpt
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.logdb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.rdb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.tdb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp0.ddb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp_merge.kpt
.......................\..\PIPE_LINING_CPU_TEAM_24.db_info
.......................\..\PIPE_LINING_CPU_TEAM_24.eco.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.eds_overflow
.......................\..\PIPE_LINING_CPU_TEAM_24.fit.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.hier_info
.......................\..\PIPE_LINING_CPU_TEAM_24.hif
.......................\..\PIPE_LINING_CPU_TEAM_24.lpc.html
.......................\..\PIPE_LINING_CPU_TEAM_24.lpc.rdb
.......................\..\PIPE_LINING_CPU_TEAM_24.lpc.txt
.......................\..\PIPE_LINING_CPU_TEAM_24.map.bpm
.......................\..\PIPE_LINING_CPU_TEAM_24.map.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.map.ecobp
.......................\..\PIPE_LINING_CPU_TEAM_24.map.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.map.kpt
.......................\..\PIPE_LINING_CPU_TEAM_24.map.logdb
.......................\..\PIPE_LINING_CPU_TEAM_24.map.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.map_bb.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.map_bb.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.map_bb.logdb
.......................\..\PIPE_LINING_CPU_TEAM_24.pre_map.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.pre_map.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.rpp.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.rtlv.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.rtlv_sg.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.rtlv_sg_swap.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.sgate.rvd
.......................\..\PIPE_LINING_CPU_TEAM_24.sgate_sm.rvd
.......................\..\PIPE_LINING_CPU_TEAM_24.sgdiff.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.sgdiff.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.sim.cvwf
.......................\..\PIPE_LINING_CPU_TEAM_24.sim.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.sim.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.sim.rdb
.......................\..\PIPE_LINING_CPU_TEAM_24.sld_design_entry.sci
.......................\..\PIPE_LINING_CPU_TEAM_24.sld_design_entry_dsc.sci
.......................\..\PIPE_LINING_CPU_TEAM_24.syn_hier_info
.......................\..\PIPE_LINING_CPU_TEAM_24.tan.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.tis_db_list.ddb
.......................\..\PIPE_LINING_CPU_TEAM_24.tmw_info
.......................\..\PIPE_LINING_CPU_TEAM_24_global_asgn_op.abo
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.asm.qmsg
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.fit.qmsg
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.map.qmsg
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.qmsg
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.sim.qmsg
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.tan.qmsg
.......................\..\wed.wsf
.......................\DM.v
.......................\DM.v.bak
.......................\exec.v
.......................\exec.v.bak
.......................\extender.v
.......................\extender.v.bak
.......................\ifetch.v
..............