文件名称:dma_hussam
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verilog code for dma
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下载文件列表
25.3.10\access_tasks.v
.......\dma.v
.......\dma_tb.v
.......\DPRAM512x32.v
.......\fifo.v
.......\interrupt.v
.......\main_dma.v
.......\parameters.v
.......\registers.v
.......\reset_and_error_tasks.v
.......\tests.v
.......\dma_tb.cr.mti
.......\work\_info
.......\....\.temp\vlogs93rzj
.......\....\.....\vlogtw6xj9
.......\....\.....\vlogjwf9aa
.......\....\.....\vlog8m80rd
.......\....\_vmake
.......\....\dma\_primary.vhd
.......\....\...\verilog.psm
.......\....\...\verilog.prw
.......\....\...\_primary.dbs
.......\....\...\_primary.dat
.......\....\..._tb\_primary.vhd
.......\....\......\verilog.psm
.......\....\......\verilog.prw
.......\....\......\_primary.dbs
.......\....\......\_primary.dat
.......\....\@d@p@r@a@m512x32\_primary.vhd
.......\....\................\verilog.psm
.......\....\................\verilog.prw
.......\....\................\_primary.dbs
.......\....\................\_primary.dat
.......\....\fifo\_primary.vhd
.......\....\....\verilog.psm
.......\....\....\verilog.prw
.......\....\....\_primary.dbs
.......\....\....\_primary.dat
.......\....\interrupt\_primary.vhd
.......\....\.........\verilog.psm
.......\....\.........\verilog.prw
.......\....\.........\_primary.dbs
.......\....\.........\_primary.dat
.......\....\addr_gen\_primary.vhd
.......\....\........\verilog.psm
.......\....\........\verilog.prw
.......\....\........\_primary.dbs
.......\....\........\_primary.dat
.......\....\mem_cntrl_fsm\_primary.vhd
.......\....\.............\verilog.psm
.......\....\.............\verilog.prw
.......\....\.............\_primary.dbs
.......\....\.............\_primary.dat
.......\....\.ain_dma\_primary.vhd
.......\....\........\verilog.psm
.......\....\........\verilog.prw
.......\....\........\_primary.dbs
.......\....\........\_primary.dat
.......\....\registers\_primary.vhd
.......\....\.........\verilog.psm
.......\....\.........\verilog.prw
.......\....\.........\_primary.dbs
.......\....\.........\_primary.dat
.......\dma_Tests_Report.dat
.......\registers.v.bak
.......\vsim.wlf
.......\tests.v.bak
.......\dma_tb.v.bak
.......\dmat_tb.cr.mti
.......\work\_temp
.......\....\dma
.......\....\dma_tb
.......\....\@d@p@r@a@m512x32
.......\....\fifo
.......\....\interrupt
.......\....\addr_gen
.......\....\mem_cntrl_fsm
.......\....\main_dma
.......\....\registers
.......\work
25.3.10
DMA FDR.ppt
.......\dma.v
.......\dma_tb.v
.......\DPRAM512x32.v
.......\fifo.v
.......\interrupt.v
.......\main_dma.v
.......\parameters.v
.......\registers.v
.......\reset_and_error_tasks.v
.......\tests.v
.......\dma_tb.cr.mti
.......\work\_info
.......\....\.temp\vlogs93rzj
.......\....\.....\vlogtw6xj9
.......\....\.....\vlogjwf9aa
.......\....\.....\vlog8m80rd
.......\....\_vmake
.......\....\dma\_primary.vhd
.......\....\...\verilog.psm
.......\....\...\verilog.prw
.......\....\...\_primary.dbs
.......\....\...\_primary.dat
.......\....\..._tb\_primary.vhd
.......\....\......\verilog.psm
.......\....\......\verilog.prw
.......\....\......\_primary.dbs
.......\....\......\_primary.dat
.......\....\@d@p@r@a@m512x32\_primary.vhd
.......\....\................\verilog.psm
.......\....\................\verilog.prw
.......\....\................\_primary.dbs
.......\....\................\_primary.dat
.......\....\fifo\_primary.vhd
.......\....\....\verilog.psm
.......\....\....\verilog.prw
.......\....\....\_primary.dbs
.......\....\....\_primary.dat
.......\....\interrupt\_primary.vhd
.......\....\.........\verilog.psm
.......\....\.........\verilog.prw
.......\....\.........\_primary.dbs
.......\....\.........\_primary.dat
.......\....\addr_gen\_primary.vhd
.......\....\........\verilog.psm
.......\....\........\verilog.prw
.......\....\........\_primary.dbs
.......\....\........\_primary.dat
.......\....\mem_cntrl_fsm\_primary.vhd
.......\....\.............\verilog.psm
.......\....\.............\verilog.prw
.......\....\.............\_primary.dbs
.......\....\.............\_primary.dat
.......\....\.ain_dma\_primary.vhd
.......\....\........\verilog.psm
.......\....\........\verilog.prw
.......\....\........\_primary.dbs
.......\....\........\_primary.dat
.......\....\registers\_primary.vhd
.......\....\.........\verilog.psm
.......\....\.........\verilog.prw
.......\....\.........\_primary.dbs
.......\....\.........\_primary.dat
.......\dma_Tests_Report.dat
.......\registers.v.bak
.......\vsim.wlf
.......\tests.v.bak
.......\dma_tb.v.bak
.......\dmat_tb.cr.mti
.......\work\_temp
.......\....\dma
.......\....\dma_tb
.......\....\@d@p@r@a@m512x32
.......\....\fifo
.......\....\interrupt
.......\....\addr_gen
.......\....\mem_cntrl_fsm
.......\....\main_dma
.......\....\registers
.......\work
25.3.10
DMA FDR.ppt