文件名称:Digital-Clock

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.41mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • lich*****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

基于FPGA 的数字时钟SHEJI-Digital Clock in the FPGA      
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Digital Clock\Cnt24.bsf

.............\Cnt24.v

.............\Cnt24.v.bak

.............\Cnt60.bsf

.............\Cnt60.v

.............\Cnt60.v.bak

.............\Dec7S.bsf

.............\Dec7S.v

.............\DigClock.sim.rpt

.............\DigClock.bdf

.............\DigClock.done

.............\DigClock.dpf

.............\Cnt24_0.bdf

.............\DigClock.fit.smsg

.............\DigClock.fit.summary

.............\DigClock.map.rpt

.............\DigClock.flow.rpt

.............\DigClock.map.summary

.............\DigClock.pin

.............\DigClock.qpf

.............\DigClock.qsf

.............\Cnt24_0.vwf

.............\DigClock.sof

.............\DigClock.fit.rpt

.............\DigClock.asm.rpt

.............\Dis.bsf

.............\Dis.v

.............\Dis.v.bak

.............\Dis_vhd.bsf

.............\Dis_vhd.vhd

.............\Dis_vhd.vhd.bak

.............\db\DigClock.asm.qmsg

.............\..\DigClock.tis_db_list.ddb

.............\..\DigClock.cbx.xml

.............\..\prev_cmp_DigClock.map.qmsg

.............\..\prev_cmp_DigClock.qmsg

.............\..\DigClock.cmp.ecobp

.............\..\DigClock.sim.qmsg

.............\..\DigClock.map.qmsg

.............\..\DigClock.sim.hdb

.............\..\prev_cmp_DigClock.sim.qmsg

.............\..\DigClock.sim.cvwf

.............\..\DigClock.eds_overflow

.............\..\wed.wsf

.............\..\DigClock.db_info

.............\..\prev_cmp_DigClock.fit.qmsg

.............\..\DigClock.fit.qmsg

.............\..\DigClock.hier_info

.............\..\DigClock.hif

.............\..\DigClock.sim.rdb

.............\..\DigClock.cmp.logdb

.............\..\DigClock.map.ecobp

.............\..\DigClock.rtlv_sg_swap.cdb

.............\..\DigClock.pre_map.cdb

.............\..\DigClock.map_bb.logdb

.............\..\DigClock.map_bb.hdbx

.............\..\DigClock.sgdiff.cdb

.............\..\DigClock.sta.qmsg

.............\..\DigClock.eco.cdb

.............\..\DigClock.psp

.............\..\DigClock.root_partition.cmp.atm

.............\..\DigClock.root_partition.cmp.dfp

.............\..\DigClock.root_partition.cmp.hdbx

.............\..\DigClock.root_partition.cmp.logdb

.............\..\DigClock.root_partition.cmp.rcf

.............\..\DigClock.root_partition.map.atm

.............\..\DigClock.root_partition.map.hdbx

.............\..\prev_cmp_DigClock.asm.qmsg

.............\..\DigClock.sgdiff.hdb

.............\..\prev_cmp_DigClock.sta.qmsg

.............\..\DigClock.rtlv.hdb

.............\..\DigClock.pre_map.hdb

.............\..\DigClock.cmp.bpm

.............\..\DigClock.tmw_info

.............\..\DigClock.rtlv_sg.cdb

.............\..\DigClock.root_partition.map.info

.............\..\DigClock.map_bb.cdb

.............\..\DigClock.map_bb.hdb

.............\..\DigClock.syn_hier_info

.............\..\DigClock.tiscmp.slow_1200mv_85c.ddb

.............\..\DigClock.tiscmp.fastest_slow_1200mv_85c.ddb

.............\..\DigClock.sld_design_entry_dsc.sci

.............\..\DigClock.map.cdb

.............\..\DigClock.map.hdb

.............\..\DigClock.map.logdb

.............\..\DigClock.map.bpm

.............\..\DigClock.asm_labs.ddb

.............\..\DigClock.cmp.cdb

.............\..\DigClock.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd

.............\..\DigClock.sta_cmp.8_slow_1200mv_85c.tdb

.............\..\DigClock.signalprobe.cdb

.............\..\DigClock.cmp.hdb

.............\..\DigClock.sta.rdb

.............\..\DigClock.cmp.rdb

.............\..\DigClock.tiscmp.slow_1200mv_0c.ddb

.............\..\DigClock.tiscmp.fastest_slow_1200mv_0c.ddb

.............\..\DigClock.tiscmp.fast_1200mv_0c.ddb

.............\..\DigClock.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd

.............\..\DigClock.sld_design_entry.sci

.............\DigClock.sta.summary

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