文件名称:FPGA--SDRAM
介绍说明－－下载内容均来自于网络，请自行研究使用
SDRAM:Synchronous Dynamic Random Access Memory- 同步动态随机存储器，同步是指 Memory工作需要同步时钟，内部的命令的发送与数据的传输都以它为基准；动态是指存储阵列需要不断的刷新来保证数据不丢失；随机是指数据不是线性依次存储，而是自由指定地址进行数据读写。
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FPGA读写SDRAM的实例\使用说明请参看右侧注释====〉〉.txt
...................\vga_system\altpll0.bsf
...................\..........\altpll0.ppf
...................\..........\altpll0.v
...................\..........\altpll0_bb.v
...................\..........\altpll0_wave0.jpg
...................\..........\altpll0_waveforms.html
...................\..........\burst_0.v
...................\..........\cpu.v
...................\..........\cpu_bht_ram.mif
...................\..........\cpu_dc_tag_ram.mif
...................\..........\cpu_ic_tag_ram.mif
...................\..........\cpu_jtag_debug_module.v
...................\..........\cpu_jtag_debug_module_wrapper.v
...................\..........\cpu_mult_cell.v
...................\..........\cpu_ociram_default_contents.mif
...................\..........\cpu_rf_ram_a.mif
...................\..........\cpu_rf_ram_b.mif
...................\..........\cpu_test_bench.v
...................\..........\FreeDevDAV.tcl
...................\..........\freedev_vga_inst.v
...................\..........\jtag_uart.v
...................\..........\led_pio.v
...................\..........\sdram.v
...................\..........\sdram_test_component.v
...................\..........\sopc_add_qip_file.tcl
...................\..........\sopc_builder_log.txt
...................\..........\sysid.v
...................\..........\sys_clk_timer.v
...................\..........\vga_fifo.v
...................\..........\vga_sys.bsf
...................\..........\vga_sys.ptf
...................\..........\vga_sys.ptf.bak
...................\..........\vga_sys.ptf.pre_generation_ptf
...................\..........\vga_sys.qip
...................\..........\vga_sys.sopc
...................\..........\vga_sys.v
...................\..........\vga_system.asm.rpt
...................\..........\vga_system.bdf
...................\..........\vga_system.done
...................\..........\vga_system.fit.rpt
...................\..........\vga_system.fit.smsg
...................\..........\vga_system.fit.summary
...................\..........\vga_system.flow.rpt
...................\..........\vga_system.jdi
...................\..........\vga_system.map.rpt
...................\..........\vga_system.map.smsg
...................\..........\vga_system.map.summary
...................\..........\vga_system.pin
...................\..........\vga_system.pof
...................\..........\vga_system.qpf
...................\..........\vga_system.qsf
...................\..........\vga_system.qws
...................\..........\vga_system.sof
...................\..........\vga_system.tan.rpt
...................\..........\vga_system.tan.summary
...................\..........\vga_system_assignment_defaults.qdf
...................\..........\vga_sys_generation_script
...................\..........\vga_sys_log.txt
...................\..........\vga_sys_setup_quartus.tcl
...................\..........\使用说明请参看右侧注释====〉〉.txt
...................\..........\vga_sys_sim\atail-f.pl
...................\..........\...........\dummy_file
...................\..........\...........\jtag_uart_input_mutex.dat
...................\..........\...........\jtag_uart_input_stream.dat
...................\..........\...........\jtag_uart_output_stream.dat
...................\..........\software\vga_control_syslib\.cdtbuild
...................\..........\........\..................\.cdtproject
...................\..........\........\..................\.project
...................\..........\........\..................\readme.txt
...................\..........\........\..................\system.stf
...................\..........\........\..................\.settings\org.eclipse.cdt.core.prefs
...................\..........\........\..................\.........\org.eclipse.cdt.managedbuilder.core.prefs
...................\..........\........\...........\.cdtbuild
...................\..........\........\...........\.cdtproject
...................\..........\........\...........\.project
...................\..........\........\...........\ap