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32×4bitRAM
- 32×4bit 的RAM设计。VHD语言。能在ISE上仿真。-32 × 4bit the RAM design. VHD language. The simulation in ISE.
LCD1602-4BIT
- 液晶 LCM 1602 的四位并口驱动源程序-LCD LCM 1602 the four parallel port driver source
HTADPCM4
- 对16bit的WindowPCM的语音文件进行压缩为4BIT的文件,压缩率约为75％,可大幅缩减所占用的空间.-The WindowPCM of 16bit audio files for 4bit compressed files, compression rate is about 75, can be substantially reduced by the space occupied.
1602LCD
- 用EPM1270实现的1602液晶驱动Verilog-EPM1270 achieved by 1602 LCD driver Verilog
fourbitincrement
- 用VHDL编译的源代码，4bit加一器，输入一个4位二进制数自动加一，解压后直接用Quartus打开project即可-Compiled with VHDL source code, 4bit-plus-one, and enter a 4-bit binary number plus one automatically, after extracting the direct use of Quartus can open the p
Viterbi_dec
- GSM信道译码 测试条件:上行DSP时钟@169MHz--->(STM #0xC007,CLKMD) SDCCH---->抽取比特固定为1bit需要时间1.2ms(viterbi解码算法)||1.06ms(非viterbi译码算法) 抽取比特如果为4bit需要时间2.8ms(viterbi解码算法)||2.72ms(非viterbi-GSM channel decoder test con
pld
- 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中
imagehide
- 直接4bit替换法的图像伪装技术以及对第四bit考察的matlab代码，其中需要两幅大小一样的图像-Direct 4bit image replacement method camouflage technologies, as well as inspection of the fourth bit of matlab code, one of two required size images
MAC_4_CSA
- MAC-4bit verilog source code with CSA style
lcd_driver_4bit
- it is a 4-bit lcd driver written in verilog .it will work on spartan 3 xilini devices.
4BIT_ALU
- this program performs the functonality of 4 bit alu
CLCD4
- ATMEL 128 CLCD 4BIT CONTROL
adder
- 加法器 可做4BIT的運算 用直接語言撰寫-Adder computing can 4BIT
multiplier_8_bit
- This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multiplier 8bit, and test bench file. This is a unsigned type.-This is 8bit multiplier VHDL code. It s consist of full adder,
WallaceTreeMultiplier
- Wallace Tree Multiplier in VHDL for 4bit operation fully using structural language
VHDL
- VHDL的4bit*4bit的有符号无符号的乘法除法实现-VHDL unsigned signed to achieve the multiplication division
exa130302_ab
- 设计IIR滤波器,对滤波器系数按4bit和5bit量化。-Design of IIR filter coefficients of the filter and 5bit quantified by 4bit.
program
- 设计实现4bit FIFO, 数据深度为8， 产生满， 空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to
display
- ASM LCD 4-bit interface used, all pins connected to port b
4bitALU
- 4 bit ALU 设计功能仿真和门级仿真结果 -4 bit ALU