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uartok
- 采用verilog编写的串口通信程序，采用了状态机设计！程序简单，消耗资源少-Serial communication written by verilog hdl. It is designed with FSM. The program is simple,and consume resource is few.
ClkScan
- 此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块，一个提供同步信号（H_SYNC和V_SYNC）及像素位置信息；另一个接收像素位置信息，并输出颜色信号。这样便于进行图形修改，同时也容易实现- This design uses Verilog the HDL hardware language design, realizes on the palm space development b
qdq_new
- 采用Verilog HDL设计,在掌宇智能开发板上得到实现 根据抢答器的原理，整个电路可划分为三部分：采样电路、门控电路和译码电路- Uses Verilog the HDL design, obtains the realization basis on the palm space intelligence development board to snatch the answering principle, the en
pci 的vhdl 源代码
- pci 的vhdl 源代码-The source code of PCI VHDL.
CRC校验参考设计_xilinx_vhdl
- 可配置CRC参考设计 xilinx提供的VHDL-configurable CRC reference design for Xilinx VHDL
activehdl6.2的crack
- activehdl的 crack，高手破解 ，很多人用过 绝对好用，如有需要者可以下载使用-activehdl the crack, crack experts, many people used the absolute ease of use, and if necessary can be used to download
abel-hdl
- lattice的abel-hel开发文档，对cpld开发的朋友会有用-the lattice-CAS documentation, the development of cpld be friends with
Verilog DHL数字钟
- 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
micro uart
- 硬件uart源程序verilog HDL，即相关文档-hardware UART Verilog HDL source, that the relevant documents
dds_vhdl
- dds的vhdl实现,主要包括正弦波、三角波和锯齿波的产生-dds achieve the VHDL, including sine, triangle wave, and the selection ramp
数字系统设计教程4_9
- vhdl的几个编程，4位除法器的设计和原理说明，还有8位CPU设计-VHDL programming, the four division and the design principle that there are eight CPU Design
数字系统设计相关
- 这是有关VHDL的相关源代码，有简易CPU、加法器、除法器、计数器等-This is the relevance of the VHDL source code, a simple CPU, Adder, Divider, counters, etc.
ddsVHDL
- 基于VHDL的DDS设计，在QUTURS2zhon仿真通过-based on the DDS VHDL design and simulation through the QUTURS2zhon
2D_convolution
- 二维卷积运算之C语言实现 若x为N1*M1的二维信号，y为N2*M2的二维信号，则卷积为(N1+N2-1)*(M1+M2-1)的信号-2D convolution operators on C language if x N1* M1 to the two-dimensional signal y* M2 N2 for the two-dimensional signal, convolution (N1 N2-1)* (M1 M2
出租车计价器VHDL程序与仿真
- 出租车计价器VHDL程序与仿真，vhdl源码，对设计这方面的同志们具有很好的参考价值-Taximeter procedures and VHDL simulation, VHDL source code, to this regard, the design of the comrades who have a good reference value! !
自动售货机VHDL程序与仿真
- 自动售货机VHDL程序与仿真，源码，具有很高的参考价值！-vending machines procedures and VHDL simulation source code, the high reference value!
MPSK调制与解调VHDL程序与仿真
- MPSK调制与解调VHDL程序与仿真,具有很高的参考价值!!vhdl代码!-MPSK modulation and demodulation process and VHDL simulation, high reference value! ! VHDL code!
异步FIFO存储器的控制设计
- 异步FIFO控制器的设计 主要用于异步先进先出控制器的设计。 所用语言Verilog HDL.-asynchronous FIFO controller design for the main asynchronous FIFO controller design. The language used Verilog HDL.