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Verilog硬件描述语言教程
- Verilog硬件描述语言教程.rar--Verilog hardware descr iption language tutorial.
ethernet_verilog
- 这是一个很好的Verilog 编写的8位RISC CPU源码(可做为MCU),并且包括完整的C 语言的测试代码。-This is a very good preparation Verilog 8-bit RISC CPU source (available as MCU), and includes a complete C language test code.
Verilog-golden
- VHDL黄金版,本人费了九牛才找到,帮助初学者入门-VHDL version, I spent nine cattle to find help beginners entry
alu
- 硬件设计vhdl_cpu1,1. You may copy and distribute verbatim copies of this core, as long -- as this file, and the other associated files, remain intact and -- unmodified. Modifications are outlined below.-hardware design vhdl_
指数平滑法预测数据
- 指数平滑法预测数据 输入: k--平滑周期 * n--原始数据个数 * m--预测步数 * alfa--加权系数 * x--指向原始数据数组指针 * 输出: s1--返回值为指向一次平滑结果数组指针 * s2--返回值为指向二次指数平滑结果数组指针 * s3--返回值为指向三次指数平滑结果数组指针 * xx--返回值为指向预测结果数组指针-exponential smoothing forecast data entry : k-- s
source9-10
- verilog hdl教程135例:verilog hdl语言类似于C语言,便于学习。本文档带有源代码,9-10章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 9-10
source11-12
- verilog hdl教程135例:verilog hdl语言类似于C语言,便于学习。本文档带有源代码,11-12章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code 11-10-12 Cap
risc_cpu
- 这是一个Verilog HDL编写的RISC cpu的程序,该程序共10个子程序,实现了简单的RISC cpu,可供初学者参考,学习硬件描述语言,及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which came true the simple RISC cpu.
多个Verilog的代码
- 多个VHDL编码的例题,详细的电路图介绍,还有流程图-many examples of VHDL code, the particular introduction of circuit diagram and flow chart
数据结构c描述习题集答案
- 减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能,可以进行自增和自减计数,其计数周期为2^N(N为二进制位数)。 二、设计原理 输入/输出说明: d:异步置数数据输入; q:当前计数器数据输出; clock:时钟脉冲; count_en:计数器计数使能控制(1:计数/0:停止计数); updown:计数器进行自加/自减运算控制(1:自加/0:自减); load_d-a counte
Game_HLD3
- 基于fpga和xinlinx ise的小游戏的vhdl程序,希望对你有所帮助!-xinlinx and they simply based on the small game and ideally the VHDL process, and I hope to help you!
Mouse_HLD3
- 基于fpga和xinlinx ise的鼠标应用vhdl程序,希望对你有所帮助!-and they simply based on the mouse xinlinx ideally VHDL application procedures, and I hope to help you!
可编程逻辑系统的VHDL设计技术_0
- 可编程逻辑系统的VHDL设计技术,该本书首先对VHDL语言进行了阐述,然后用alter公司的产品进行举例!-programmable logic system VHDL design technology, the first book of VHDL expounded, and then alter the company's products, for example!
8051verilog源码
- 8051的Verilog-Verilog OF 8051
pinglvhecheng
- 程序用VHDL实现: 频率合成,DDS 主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM
VHDL tutor n exam
- verilog hdl. for igginner. tutorial in word file1 KAMPATE
ddsall
- DDS的vhdl语言源程序实现 该程序可实现1HZ频率步进-DDS source VHDL language to achieve the program can be realized 1HZ frequency Step
I2C总线控制器 Xilinx提供
- 用Verilog HDL实现I2C总线功能,对I2C总线有很大帮助-I2C bus contrll functions implemented by Verilog HDL.