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数字频率合成器的FPGA实现
- 在EDA中，基于数字频率合成器的FPGA实现-in EDA, based Digital Frequency Synthesizer FPGA
TLC2543and80C196interface
- 单片机不具有SPI或相同能力的接口，为了便于与TLC2543接口，采用软件合成SPI操作，本文给出了用单片机HSO口模拟SPI接口时序的方法，对程序稍加改动就可适用于其它带SPI接口的器件.附加有c语言程序-SCM is not the same capacity or SPI interface, in order to facilitate and TLC2543 interface, using software synthesi
HTS-2.0RC2_for_HTK-3.4-alpha.patch
- HTS-2.0RC2，HTS语音合成器的最新测试版。首先需要安装HTK3.4。与HTS1.1相比功能更加强大。嵌入式训练算法更新。-HTS - 2.0RC2 HTS voice synthesizer to the latest test version. HTK3.4 first need to install. HTS1.1 compared with the more powerful functions. Embedded tr
dds_fpga
- DDS在现在运用月来越广泛，在相对带宽、频率转换时间、相位连续性、正交输出、高分辨力以及集成化等方面都远远超过了传统频率合成技术所能达到的水平，为系统提供了优于模拟信号源的性能。利用DDS技术可以很方便地实现多种信号。在FPGA上实现的DDS-DDS now to the use of more extensive relative bandwidth, frequency conversion time, phase continui
DDScom
- 直接式数字锁相环频率合成器.用ELANIX公司SYSTEMVIEW运行.-direct digital PLL frequency synthesizer. SYSTEMVIEW ELANIX companies with operations.
ADAPTC
- 术是继直接频率合成和间接频率合成之后，随着数字集成电路和微电子技术的发展而迅速发展起来的第三代频率合成技术。DDS技术具有相对带宽宽、频-operation is the direct and indirect frequency synthesizer frequency synthesis, With digital integrated circuits and microelectronic technology develop
adaptIDFIR
- 术是继直接频率合成和间接频率合成之后，随着数字集成电路和微电子技术的发展而迅速发展起来的第三代频率合成技术。DDS技术具有相对带宽宽、频-operation is the direct and indirect frequency synthesizer frequency synthesis, With digital integrated circuits and microelectronic technology develop
wide_interval_hop_sequence
- kuanjiange_seq.m 基于对偶频带法和m序列，产生一个宽间隔跳频序列。 kuanjiange_seqencezu.m 基于对偶频带法和m序列，产生一个宽间隔跳频序列族。 注：其中的m序列是利用三个非相邻级控制频率合成器构造 L_G模型。-kuanjiange_seq.m based on dual band m sequence, have a wide interval frequency hoppin
cpldtodds
- dds信号发生器程序设计，框图，基于CPLD控制的DDS数字频率合成器设计-dds signal generator program design, block diagram, the CPLD based on DDS Digital Frequency Synthesizer Design
FrequencySynthesisbyPhaseLock
- 书籍频综和锁相环的Matlab源代码，对频综和锁相环的设计很有帮助；-Books PLL Frequency Synthesizer and the Matlab source code for PLL Frequency Synthesizer Design and helpful
daimahekuangtu
- ，用MATLAB实现快跳频通信系统的仿真。主要应用了SIMULINK和COMMUNICATION BLOCKETS两个模块。整个设计包括了信源产生部分、发送部分、跳频调制部分、信道部分、接收部分和结果分析部分共六个模块，核心技术是伪随机序列的产生和频率合成器的设计，而关键技术是收发两端的伪随机码元的同步。伪随机码的产生用S－函数编程来开发自己的SIMULINK模块。同步的实现是收发两端采用相同的扩频脉冲触发。而且在设计中每个模块都采用了
dangonghujiaofasheji
- 发射部分采用锁相环式频率合成器技术， MC145152和MC12022芯片组成锁相环，将载波频率精确锁定在35MHz，输出载波的稳定度达到4×10-5，准确度达到3×10-5，由变容二极管V149和集成压控振荡器芯片MC1648实现对载波的调频调制；末级功放选用三极管2SC1970，使其工作在丙类放大状态，提高了放大器的效率，输出功率达到设计要求。-Part of the launch phase-locked loop frequen
accumulate222
- 相位累加器，即DDS频率合成器的MATALB实现，采用M文件编写的S函数-Phase accumulator, that is, the DDS frequency synthesizer MATALB realized, the use of M' s S function documentation
fmsynth
- MINI FM miniport驱动，开发工具：winddk-This sample is a MIDI FM miniport driver. This sample provides an interface to a device that implements OPL3-style FM synthesis. The MIDI port driver serves as a wrapper for this miniport d
FPGA-DDC
- 基于FPGA的直接数字频率合成器的设计和实现。-FPGA-Based Direct Digital Frequency Synthesizer Design and Implementation.
ddfsdemo
- 直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL p
ddfs
- 直接数字频率合成器，整个工程文件都在，仿真也有，直接就能用。-Direct digital frequency synthesizer, the entire project file are in the simulation is also directly be able to use.
music-synthesizer-for-android
- Music Synthesizer for Android
Fast-Switching-PLL-Synthesizer
- A 10μs Fast Switching PLL Synthesizer for a GSM/EDGE Base-Station.介绍快速跳频锁相环的非常好的一篇文章！-A 10μs Fast Switching PLL Synthesizer for a GSM/EDGE Base-Station.A very good article on the fast frequency hopping phase-locked loop
DE2_115_Synthesizer
- SOUND DEMONSTRATION AND SYNTHESIZER