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HTS-2.0RC2_for_HTK-3.4-alpha.patch
- HTS-2.0RC2，HTS语音合成器的最新测试版。首先需要安装HTK3.4。与HTS1.1相比功能更加强大。嵌入式训练算法更新。-HTS- 2.0RC2 HTS voice synthesizer to the latest test version. HTK3.4 first need to install. HTS1.1 compared with the more powerful functions. Embedded tra
ADAPTC
- 术是继直接频率合成和间接频率合成之后，随着数字集成电路和微电子技术的发展而迅速发展起来的第三代频率合成技术。DDS技术具有相对带宽宽、频-operation is the direct and indirect frequency synthesizer frequency synthesis, With digital integrated circuits and microelectronic technology develop
adaptIDFIR
- 术是继直接频率合成和间接频率合成之后，随着数字集成电路和微电子技术的发展而迅速发展起来的第三代频率合成技术。DDS技术具有相对带宽宽、频-operation is the direct and indirect frequency synthesizer frequency synthesis, With digital integrated circuits and microelectronic technology develop
adaptIDFIRW
- 术是继直接频率合成和间接频率合成之后，随有4～20倍可编程时钟乘法电路，系统最高时钟可达300 MHz,输出频率可达120 MHz，频率转化速度小于1μs。内部有12位D/A转化器、48位可编程频率寄存器和-Surgery is the direct and indirect frequency synthesizer after synthesis, with 4 ~ 20 times the programmable clock m
wide_interval_hop_sequence
- kuanjiange_seq.m 基于对偶频带法和m序列，产生一个宽间隔跳频序列。 kuanjiange_seqencezu.m 基于对偶频带法和m序列，产生一个宽间隔跳频序列族。 注：其中的m序列是利用三个非相邻级控制频率合成器构造 L_G模型。-kuanjiange_seq.m based on dual band m sequence, have a wide interval frequency hoppin
cpldtodds
- dds信号发生器程序设计，框图，基于CPLD控制的DDS数字频率合成器设计-dds signal generator program design, block diagram, the CPLD based on DDS Digital Frequency Synthesizer Design
SIN_fashengqi
- 2006altera大赛－基于软核Nios的宽谱正弦信号发生器设计：摘要：本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA公司的 Cyclone 系列 FPGA 为数字平台，将微处理器、总线、数字频率合成器、存储器和 I/O 接口等硬件设备集中在一片 FPGA 上，利用直接数字频率合成技术、数字调制技术实现所要求波形的产生，用 FPGA 中的 ROM 储存 DDS 所需的波形表，充分利用片上资源，提
MC145163PDDS
- MC145163P型锁相频率合成器的原理与应用-MC145163P- PLL frequency synthesizer and application of the principle
DDS_sin
- 用VHDL语言实现DDS直接数字频率合成器的设计，采用正弦RAM表，可实现频率可控的正弦数字信号，编译、仿真通过。-VHDL DDS Direct Digital Frequency Synthesizer Design using sinusoidal RAM table achieve controllable frequency sinusoidal digital signal, compile, through simulat
flame09101086
- 基于51单片机的频率合成设计论文【同学捐助】 基于51单片机的频率合成设计论文【同学捐助】-SCM Frequency Synthesizer Design thesis students donor [51] Based on SCM Frequency Synthesizer Design [thesis students donor--
AD9852_DDS
- 基于DDS 芯片AD9852 的数字频率合成系统设计-based on the AD9852 DDS chip Digital Frequency Synthesizer Design
DDSchipAD9852andapplication
- 摘 要 文章介绍了直接数字频率合成器(DDS)的组成及工作原理，描述了DDS芯片 AD9852的功能特性，同时给出了AD9852在本地同步时钟中的应用。 关键词 DDS AD9852 同步时钟 -Abstract This paper presents a direct digital synthesizer (DDS) the composition and working principle, desc
zhipinmb1501
- MB1501频率合成器的分频比设置源程序-MB1501 frequency synthesizer sub-frequency source than the set
AD9850
- 此程序为AD9850（DDS）直接数字频率合成器C语言源码。用125M的有源晶振，频率无失真输出可达到40M。该程序包括FYD12864LCD显示程序加4X4矩阵键盘扫描，可步进1M，1K，和任意频率输入。及相位设置。-This procedure for the AD9850 (DDS) Direct Digital Frequency Synthesizer C language source code. With 125M act
Docs
- Creating a Voice Synthesizer Application
dds_quicklogic
- 这是quicklogic公司的直接频率合成（DDS）Verilog代码-QuickLogic Corporation This is a direct frequency synthesizer (DDS) Verilog code
adf4118
- adf4118频率合成器编程，用于选频器、选带器开发-adf4118 frequency synthesizer programming for the selected frequency, and the election with browser development
mousemtiondetection
- 在人脸检测的基础之上,对嘴部的运动表情进行分析,进行语音模拟.-In the face detection based on the movement of the mouth expression analysis, the voice synthesizer.
A.spur-free.fractional-N.pll
- A new PLL topology and a new simplified linear model are presented. The new fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a SampleJHold block. With a n
dual.band.GMSK.transmitte
- This paper presents the key circuits of a 1MHz bandwidth, 750kb/s GMSK transmitter. The fractional-N synthesizer forming the basis of the transmitter uses a combined phasefrequency detector (PFD) and digital-to-analog