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Computer-Architecture-lab5
- 计算机组成实验作业5,fpga开发板,verilog语言编写-Composition of experimental computer operating 5, fpga development board, verilog language
Computer-Architecture-lab6
- 计算机组成实验作业6,fpga开发板,verilog语言编写-Composition of experimental computer operating 6, fpga development board, verilog language
digital_clock
- verilog digital clock.四位 有计时器 有秒表 。是学生作业。 原创。 适合初步学习verilog的学生。 -verilog digital clock/4 bits/ up_down/stopwatch
display_combine
- 这是学生做的Verilog HDL 作业。 是一个数字钟。 有时钟,秒表等功能。 原创。-This is the Verilog HDL students to do the job. Is a digital clock. A clock, stopwatch and other functions. The original.
Design-exercise-M_sequence
- 通信系统电路设计练习: M序列编码/解码器的设计 作业的背景及训练目的 为了给通信专业的同学们提供一个设计实践的机会,在最短的时间段内掌握数字设计的动手能力,提高Verilog语言的使用能力,所以专门设计了这样一个难度适中的数字通信系统设计练习。本练习是根据工程实际问题提出的,但为了便于同学理解,对设计需求指标做了许多简化。希望同学们在设计范例和老师的指导下,一步一步地达到设计目标。期望同学们能在两至三周内,参考设计范
fenpin
- 开发工具是quartus II 7.0以上版本,这是一个verilog语言的分频器设计,个人作业设计,供参考学习-verilog,quartus II 7.0
compare
- 数值比较器的设计,课堂作业随堂检查,verilog语言设计,开发工具是quartus II7.0以上版本,测试仿真脚本也有-Numerical comparison of the design, classwork class check the Verilog language design, development tools is quartus II7.0 above test simulation scr ipt
DataCycle
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-cpu cpu cpu cpu cpu cpu cpu cpu
PipelineSim
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report
PIPELINE
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report
PipelineCPU
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report
lab4
- 算机组成实验作业4,fpga开发板,verilog语言编写-Composition of experimental computer operating 4, fpga development board, verilog language
cpu_1
- 用verilog设计五级CPU的框架,需要自己另行补充指令,可作为学生作业和训练内容-Five CPU with verilog design fr a mework, needs its own separate supplemental instruction can be used as student assignments and training content
Project6(finish)
- modelsim下仿真通过,用Verilog写的多周期CPU,是计算机组成原理的大作业,供学弟学妹参考。-Under modelsim simulation by using Verilog write multi-cycle CPU, is composed of a large computer operating principle for mentees reference.
8bits
- 用Verilog语言模拟的8位优先编码器,可作为课堂作业实用,是完整工程代码-Using Verilog language simulation of the 8 priority encoder, can be used as a classroom operation, is a complete code
Binary-BCD-code
- 用Verilog语言写的二进制转BCD码,可以作为课堂教学实验或者课后作业,有完整工程代码-Written in Verilog language transfer binary BCD code, can be used as a teaching experiment or the homework, a complete project code
Four-input-static-display
- 用Verilog语言写四位静态输入显示,可做课堂实验后课后作业,有完整代码-Written in Verilog language, according to the four static input to do homework after class experiment, has a complete code
hit_the_block
- 数字逻辑课程大作业,使用verilog语言编写的打砖块游戏。通过FPGA按钮控制弹板移动,反弹小球,控制小球方向,击打砖块。有VGA模块。-Digital Logic Courses big operations, the use of Verilog language brick game. The FPGA button controls the movement of the board, bounces the ball, co
text
- 作业,华中科技大学 数字电路电子线路实验1 verilog语言程序。作业源文件,大三光学与电子信息(verilog huazhongkejidaxue guangxueyudianzixinxizhuanye dianzixianlushiyan)
Single_cpu
- 单周期CPU自己课程大作业做的,亲测好用,verilog语言,适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)