搜索资源列表
VHDL.fifo
- 在网上找到的通用存储器vhdl代码库，觉得挺好用的。-the Internet to find the common memory vhdl code library, feeling very good use.
fir-vhdl
- 用Vhdl硬件描述语言编写的FIR数字滤波器-Vhdl using Hardware Descr iption Languages in preparing the FIR digital filter
SDRAM-VHDL
- SDRAM控制器的VHDL实现，pdf格式，有需要多的，联系我-SDRAM controller VHDL, pdf format, it needs more, Contact
cpu-16-vhdl
- 16位cpu的vhdl源代码。 自己看看，没有注释。-16 cpu vhdl the source code. See for yourself, not Notes.
DS18B20+VHDL
- 用VHDL语言实现的控制DS18B20构成测温仪表的程序，包含了全部代码，可显示最高精度-with VHDL control DS18B20 constitute Thermometer procedures, contains all the code will show that the most high-precision
(7)VHDL
- 是老师介绍的一些关于vhdl设计的源程序及讲解，感觉还不错，要不你们-teachers on the design of some of the source code vhdl and briefings, the feeling was pretty good, you want to try
VHDL
- 基才VHDL状态机设计的智能交通控制灯 设计 有需要的可以看一下-only VHDL-based state machine design and intelligent traffic control lights need to design can look at the
VHDL
- 基才VHDL状态机设计的智能交通控制灯 有需要的可以看一下-only VHDL-based state machine design and intelligent traffic control lights need to see what
mc8051-VHDL
- VHDL实现 8051 CPU核 Oregano Systems 8-bit Microcontroller IP-Core-VHDL 8051 CPU nuclear Oregano Systems 8-bit Mic rocontroller IP-Core
DCT-vhdl
- 这是一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT)算法,采用VHDL实现-This is a two-dimensional 8* 8 discrete cosine transform (DCT) and inverse transform (IDCT) algorithms using VHDL realize
VHDL
- vhdl语言设计资料，学习FPGA设计的好书籍。-vhdl脫茂脩脭脡猫 录 脝 脳 脢脕脧 拢 卢 脩 搂 脧 掳 FPGA脡猫 录 脝渭脛 潞 脙脢茅 录 庐 隆 拢
filter-vhdl-code
- filter-vhdl-code.rar为滤波器的完整VHDL程序，可用于IIR与FIR滤波器的仿真与验证实现，包括代码综合。使用版本为ISE6.3.-filter-vhdl-code.rar for the integrity of filter VHDL procedures, can be used for IIR and FIR filters realize simulation and verification, inclu
VHDL-vga_core(vhdl)
- VHDL-vga_core(vhdl).rar FPGA上实现 VGA的IP（VHDL）-VHDL-vga_core (vhdl). RarFPGA realize VGA on the IP (VHDL)
PS2-IP-CORE-VHDL
- 一个PS2 IP CORE(VHDL) for FPGA-A PS2 IP CORE (VHDL) for FPGA
VHDL
- 几个ＶＨＤＬ的编程实例-Several examples of VHDL programming
ref-sdr-sdram-vhdl
- FPGA连接SDRAM的源程序，VHDL语言实现，功能基本完全。应用效果好。-FPGA connected SDRAM source, VHDL language, the basic function fully. Application effective.
vhdl--timer
- 关于基于fpga的，数字化时钟vhdl实现源程序，推荐大家下载仿真实现。-On the FPGA-based, digital clock source VHDL realize recommend everyone to download simulation.
VHDl
- VHDL数字控制系统设计范例，PDG格式的，希望对大家有用！-VHDL Examples of digital control system design, PDG format, in the hope that useful to everybody!
VHDL-timer
- 这是关于VHDL时钟的源代码，欢迎大家下载交流！-This is a clock on the VHDL source code, welcomed the exchange of everyone to download!
Vhdl-Parser-0.12.tar
- 這是一個VHDL的parser目前版本為0.12-This is a VHDL version of the parser is currently 0.12