搜索资源列表
URAT
- URAT的VHDL设计及时序仿真、调试、测试。含有波形图-URAT the VHDL design and timing simulation, debugging, testing. Waveform contains
FractionalPLLDesign
- 是关于sigma delta PLL设计的详细论文，论文中有具体的设计细节，并在附录中有相应的matlab、vhdl code-Is about the design of sigma delta PLL detailed papers, papers in the specific design details, and in the appendix corresponding matlab, vhdl code
WileyAdvancEdFPGADesign
- wiley2007年的新书高级FPGA设计作者是权威的设计咨询公司老总，经验之谈-wiley2007-year senior FPGA design book author is the authority of the design consulting firm CEOs, experiences
DDR_SDRAM_verilog
- DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good
seg73
- 递增方式在4位数码管上向上计数显示从0000-0001->0002……..9999….0000….0001…. -- 利用CPLD设计了一个4位十进制计数器，并用数码管显示当前计数值-Incremental approach in the four counts upward digital tube display from 0000-0001-
piano
- 电子琴程序设计,还是不错的，哈哈,有兴趣的可以载-Flower program design, or good, ha ha, are interested in can be set
SDRAMController
- SDRAM Controller 设计详细文档 ，很有参考价值！-SDRAM Controller Design of detailed documentation, a good reference!
ThreeSimulatedElevator
- 我们的课程设计,三层电梯控制器模拟程序.用verilog HDL语言编写-Our curriculum design, three-elevator controller simulation program. Verilog HDL language used
dds
- 基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
equizer
- HART协议的均衡器设计 DCT LMS 设计 + 位同步设计，仿真证明了设计的有效性-HART protocol design DCT LMS equalizer design+ Bit synchronous design, simulation proves the validity of the design
528995200441123245276683
- 基于fpga的多功能电子钟的设计非常使用希望对大家有帮助啊-FPGA-based multi-functional electronic clock design to use would like to help everyone ah
899207KEYBOARD_DEC-vhdl
- 数字平律己的设计非常实用 黄永显示早设计大方ijasd-The design of digital self-Ping Wong Wing-show as early as practical design Dafang ijasd
VHDLVERILOG
- 含近百个源码的VHDL与Verilog相对照的很不错的资料，内容涵盖了从基本说明到高级设计案例，有很强的实用性，值得一看。-Containing hundreds of VHDL and Verilog source contrast is very good information, which covers from basic instructions to advanced design of the case, there a
`5_TrafficLight
- 两路十字路口的交通灯控制的VHDL源码，毕业设计，-Two-way traffic lights at the crossroads of the VHDL source code control, graduation design,
CIC
- cpld/fpga积分梳状滤波器(CIC)设计-cpld/fpga Integral comb filter (CIC) design
HCIUART
- 蓝牙HCI—UART与并口的FPGA控制接口设计-Bluetooth HCI-UART and parallel port control interface of the FPGA design
Key-200893142940130
- 关于地铁售票的一些功能 基于自动买票的VHDL设计程序 比较经典-Subway ticket on some of the features of the VHDL-based auto-buying classic design procedure
alarm_system
- 电子闹钟：基于fpga的电子闹钟设计，采用模块化方式-Electronic alarm: FPGA-based electronic alarm clock design, modular approach
password_lock
- 电子密码锁，采用基于fpga的设计，可以设置6位密码-Electronic code locks, FPGA-based design, can be set 6 password
texi_jifei_system
- 基于fpga的出租车计费系统，采用自顶向下的设计方法-FPGA-based billing system of a taxi, using top-down design methodology