搜索资源列表
asynchronous_FIFO_01to03_CHN
- 这是设计异步FIFO的比较好的一个参考资料，希望可以对大家有用。-This is the design of better asynchronous FIFO a reference, I hope can be useful to everyone.
FPGA_clk
- FPGA异步时钟设计中的同步策略，需要-FPGA design of asynchronous clock synchronization strategy, the need for
uart
- VHDL编写的异步通信串行口设计用Quartus工具编译-VHDL prepared the design of serial asynchronous communication tool used Quartus compiler
FIFO
- 异步FIFO verilog实现 异步FIFO verilog实现 -Asynchronous FIFO verilog realize realize asynchronous FIFO verilog
motorcontrolprocedures
- 步进电机控制程序段，交流异步矢量程序，开关磁阻程序，永磁同步程序，直流无刷程序，采样SPWM程序，三相交流异步电动机SVPWM开环调速控制程序-Stepper motor control program segment, the exchange of asynchronous vector procedures, Switched Reluctance procedures, permanent magnet synchronous
Delphi_httpGet
- 能做http请求进行同步及异步返回请示页的参数-Http request can be synchronized and asynchronous page request parameters to return
CPLD
- This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 µ m CMOS process and it shows a power advantage of a factor 4 compared to a recent synchronous imple
Asyn_FIFO_Design
- 异步FIFO设计的说明文档，需要注意的问题以及源码（在文中有）。是标准的异步FIFO，可综合。-Asynchronous FIFO design documentation, as well as the need to pay attention to source code (in the text have). Is a standard asynchronous FIFO, can be integrated.
fifo-1117
- 这是异步FIFO的VHDL实现代码，已经在FPGA上通过实践证明，运行状态良好-This is the asynchronous FIFO realize the VHDL code, the FPGA has been proved through practice, running in good condition
UART
- 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial c
DSP
- 基于数字信号处理器(DSP)的异步电机直接转矩控制研究(硕士论文),含VC源代码，汇编源码以及完整硕士论文文档。-Based on digital signal processor (DSP) of the asynchronous motor direct torque control studies (master
FIFO
- 一个异步的FIFO的VERILOG程序,有测试程序-An asynchronous FIFO in Verilog procedures, test procedures have
uart
- M_UART 介绍了通用异步收发器（UART）的原理，并以可编程逻辑器件FPGA为核心控制部件，基于超高速硬件描述语言VHDL在Xilinx公司的SpartanⅡ系列的2sc200PQ208-5芯片上编程完成UART的设计。经测试，该设计完全达到了设计要求。-M_UART introduce a Universal Asynchronous Receiver Transmitter (UART) Principle and FPGA
37724082FIFO
- 基于Verilog HDL的异步FIFO设计与实现-Verilog HDL-based Asynchronous FIFO Design and Implementation
FIFO
- 通用异步FIFO设计的verilog代码，来自于opencore-Universal Asynchronous FIFO Verilog design code, from opencore
asyn_fifo
- verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
zhijiezhuanju1212
- 异步电动机直接转矩控制模型，simulink仿真模型，改进后的直接转矩控制-Asynchronous motor direct torque control model, simulink simulation model, the improved direct torque control
AS_FIFO_DESIGN_Verilog
- 使用Verilog硬件描述语言完成了一个异步FIFO的设计，供相关硬件开发人员参考。-Verilog hardware descr iption language used to complete an asynchronous FIFO design, hardware development for the relevant reference.
motor
- 三相异步电机直接起动的起动转矩较大，但起动电流也大，通常用于小功率电机。-Three-phase asynchronous motor starting torque direct start a larger, but the starting current is also large, normally used for low-power motor.