搜索资源列表
cloud
- 生成一维云模型的MATLAB程序，简单实用，可以自动生成云模型图片-Generate one-dimensional cloud model MATLAB program, simple and practical, can automatically generate cloud model picture
POV_LED_CLOCK
- 一个用单片机制作的基于POV原理的用LED显示的旋转时钟的源程序和电路图-1 Using the Microcontroller-based LED POV display using the principle of rotation of the clock source and the circuit
lcd_time
- 一个基于VHDL的多功能数字钟设计，能在LCD上显示时间，调整时间，整点报时，音乐为美妙的梁祝。-A VHDL-based design of multi-functional digital clock that can display time in the LCD, adjust the time, the whole point of time, music was wonderful Butterfly Lovers.
timeclock
- //2.10实现一个秒表功能(精确到0.01秒)，有计时按钮和复位按钮， //当安下计时按钮时开始计时，同时计时按钮文字由“开始计时”变为“停止计时”， //再次按下计时按钮停止计时同时显示文字变为“开始计时”，按下复位按钮后时间回到0:-//2.10 implement a stopwatch function (accurate to 0.01 seconds), with timing button and reset b
AlarmClock
- android 闹钟应用源代码，希望对大家学习android有重要帮助。-failed to translate
clock
- 用matlab实现clockr仿真，初学试用的小程序-Clock of matlab simulation, a small trial program beginner
AlarmClock
- 这是Android2.2闹中源码,主要讲屬 -This is Android2.2 trouble source in the f
cpu
- 用Verilog语言编写的单周期cpu，实现的指令有 add,addu,addi,addiu,sub,subu,clo,clz,xori,nor,slt,slti,sltu,sltiu,blez,j.-Verilog languages ??with single-cycle cpu, implementation instructions are add, addu, addi, addiu, sub, subu, clo, cl
digital_clock
- 可以调节时钟，分钟，秒钟信号的一个数字钟。比带有复位信号-You can adjust the clock, minutes, seconds, a digital clock signal. Compared with the reset signal
VB_clock
- 自己用VB语言编写的时钟程序。是学习VB语言的很好参考资料-Own clock using VB language program. VB language is to learn a good reference
NightClock
- 夜光始终,开源代码,颜色选择器,LED形式的始终展示-Always luminous, open source code, color picker, LED display has the form
PipelineCPU
- 用Verilog HDL语言或VHDL语言来编写，实现多周期CPU设计。能够完成以下二十二条指令。（均不考虑虚拟地址和Cache，并且默认为大端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, im
mulitcpu
- 用verilog HDL语言或者VHDL语言来编写，实现多时钟周期CPU的设计。能够完成以下二十二条指定（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs,
091220111singalcpu
- 用verilog HDL语言或者VHDL语言来编写，实现单周期CPU的设计。能够完成以下十六条指定： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs
clock
- 电子时钟的verilog代码，非常全的资料，值得一看-the clock of verilog
cloexec
- check clo flag for Linux v2.13.6.
ad-lcd-clo
- 实现电压转换并在液晶上显示，同时显示时间-Achieve voltage conversion and liquid crystal display, and the display time
CLSPSO
- 主要是利用CLO对svm进行优化，并能进行预测的matlab程序，可以运行出来，供参考-CLO is mainly used to optimize the SVM, and can predict the matlab program, you can run out for reference
LaTeX
- 适用于Springer期刊的LaTeX class。包含以下文件： readme.txt history.txt svjour3.cls usrguid3.* svglov3.clo template.tex example.* example.pdf(LaTeX class SVJour3 for Springer journals - T