搜索资源列表
vodServer
- VOD核心源码服务器端,使用Visual C++,需要一定的C++基础，和流媒体知识-VOD core-source server-side, the use of Visual C++, Needs some C++ Base, and streaming media knowledge
photo_verilog
- verilog开发的电子相册系统，是基于Altera的FPGA芯片和IP核的设计！-Verilog developed electronic album system is based on Altera s FPGA chip and IP core design!
vhdl_source
- MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx-MP3 for XPLA3 XILINX.CPLD, must XILINX use of FPGA chip, as is the Xilinx IP core
BaselineJPEGSoftwareCodecCodes
- In term project, we will take the baseline JPEG codec in ARM-based platform system as an example to practice the design flow in SoC. We divide the project into three parts, and the goal of each part is described as fol
SOPCVGAIP3090114
- 基于 SOPC 的 VGA IP 核设计-Based on SOPC the VGA IP core design
PCI-IPcoreor1k[1]
- PCI的ip core，VHDL代码，希望对大家有帮助-PCI-ip core, VHDL code, we hope to help
8086IP
- 开源CPU软核8086的源码,波兰版Verilog源码-8086 soft-core CPU revenue source, the Polish version of Verilog source code
RISC8.ZIP
- verilog RISC8 cpu CORE 8位RISC CPU 内核源码（VERILOG 版）-verilogRISC8 cpu CORE8-bit RISC CPU core source (VERILOG version)
AVR_Core.tar
- vhdl语言编写的AVR单片机IP核，里面有testbench和说明文档。-VHDL language AVR Single Chip IP core, there are Testbench and documentation.
niosIIethernetconfig
- 描述通过软核nios II在quartus环境里面实现以太网卡配置过程，。-Described through the nios II soft-core in the Quartus environment inside Ethernet card configuration process.
5df72e74-9384-4de1-a0a5-5cffd7b496e0
- 三星2440核心板公板的原理图,在三星网页上已经下在不了.费了很的劲才收集到,希望对2440的朋友有用.-Samsung 2440 public board core board schematics, the Samsung website has been in the can.劲才of a fee collected, in the hope that useful 2440 friends.
wishbone_VHDL
- wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快 成为ip通信的主流-Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of
DVRH.264
- DVR的核心技术的新突破——H.264.pdf文档-DVR& core technology breakthroughs- H .264. Pdf document
AVR_Core8F.tar
- AVR IP core writen in VHDL. It is beta version, working even with AVR studio
VERILOG_VERSION_PIC16C57
- VERILOG VERSION PIC16C57 是一个用于FPGA模拟PIC16C57的IP核，有帮助文件，介绍了如何测试使用这个IP核。用VERILOG语言编写的。-VERILOG VERSION PIC16C57 is a PIC16C57 for FPGA simulation of the IP core, has helped document describes how to test the use of the I
i2c_core
- I2C core 及testbench（verilog）-I2C core and testbench [verilog]
corejava8-V2
- Java核心技术 第八版 Java核心技术 卷2 高级篇 书中各个章节内的程序源代码。 -Core Java, 8th Edition Core Java. Volume II. Advanced Features, 8th Edition Volume II includes new sections on the StAX API, JDBC 4, compiler API, scr ipting fr a me
RT-Linu-Core
- rtlinuxRT-Linux源码 一个实时操作系统源码，很小巧。-rtlinuxRT-Linux Core
core
- linux core 函数例程，能直接运行，让你对linux 下内核函数的定义有实际的例子-linux core function routines that can run directly, so that you are under linux kernel function definition has practical example
gcc-core-3.3.3-20040217-1.tar
- mingW gcc3.3.3 源码版本3-gcc opensource virtion3.3.3