搜索资源列表
eflag-blackfin-bf533-evm_V6
- 基于BF533的开发板原理图设计, 核心芯片为 BF533，欢迎下载-BF533-based development board schematic design, the core chip for the BF533, welcome to download
ip_fft128
- 128点fft的IP核vhdl源代码，另有其控制代码。-128 point fft s IP core VHDL source code, while its control code.
262-45526-LTC2453
- Easy-to-Use, Ultra-Tiny, Differential, 16-Bit Delta Sigma ADC With I2C Interface The LTC2453 is an ultra-tiny, fully differential, 16-bit, analog-to-digital converter. The LTC2453 uses a single 2.7V to 5.5V supply and
YL2440-CORE-V10
- YL2440核心板原理图，基于S3C2440处理器，采用插卡式设计-YL2440 core board schematic diagram, based on the S3C2440 processor, using plug-in card design
567
- The paper presents the CORDIC Algorithm, which has been implemented as an virtual component (IP core) in a VHDL simulation environment. The core is packaged as a soft (VHDL) macro and it implements all transcenden-tal fu
deinter
- deinterlace的核心verilog，-deinterlace core verilog,
pci_express_crc
- PCI express CRC rtl core for Fpga/asic Designer
t51.tar
- from open core advanced intel 8051
ml505_pcie_x1_plus
- Xilinx 公司PCI Express IP核应用参考设计。通过这个样例，用户可以掌握PCI Express应用设计的一般方法，了解PCI Express的工作原理。-Xilinx Inc. PCI Express IP core reference design applications. Through this example, the user can master the application of the design
core_arm.tar
- ARM7系统IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-ARM7 System IP Core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
keyboardcontroller.tar
- 键盘控制电路IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-Keyboard control circuit IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
sdram_ctrl.tar
- SDRAM控制IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-SDRAM control IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
ARM7
- ARM开发的经典源码，包括boot,core和test程序。-ARM to develop a classic source, including the boot, core and test procedures.
uart.core.for.FPGA
- 一个UART的FPGA core，附有详细的代码阅读笔记-A UART of the FPGA core, accompanied by a detailed code of reading notes
cfft
- CFFT是一个数据宽度和点数都可配置的基4 FFT core,用VHDL实现-CFFT is a data width and the base points can be configured 4 FFT core, using VHDL realize
aes_core
- Verilog实现AES加密算法 密码模块作为安全保密系统的重要组成部分，其核心任务就是加密数据。分组密码算法AES以其高效率、低开销、实现简单等特点目前被广泛应用于密码模块的研制中。密码模块一般被设计成外接在主机串口或并口的一个硬件设备或是一块插卡，具有速度快，低时延的特点。而从整体发展趋势来看，嵌入式密码模块由于灵活，适用于多种用户终端、通信设备和武器平台，将会得到更加广泛的应用-AES encryption algorithm
LCD_Controller_Altera_MAX_II_CPLD
- 基于MAXII CPLD的对1602字符型液晶进行读写操作，其中使用了一个CFI的IP核-MAXII CPLD-based character LCD on the 1602 to read and write operation, which uses a CFI of the IP core
ARM-core
- ARM内核中断技术研究 研究生小论文 可作为研究ARM 7TEMi的专业人员参考-ARM core interrupt technology research postgraduate study of small papers can be used as reference ARM 7TEMi professionals
ARMCORE
- arm7的IP软核代码，对与研究ARM 和做FPGA开发有很大帮助！-ARM7 soft-core of the IP code, and research on the ARM and FPGA to do the development of great help!
Ethernet_verilog_ip_core
- Ethernet(以太网)verilog ip core用verilogHDL语言写的以太网软核，对学习verilog语言和以太网有很大帮助。-Ethernet (Ethernet) verilog ip core language used verilogHDL Ethernet soft-core, learning Verilog language and Ethernet are very helpful.