搜索资源列表
mmarm_EDACN
- 用FPGA实现ARM嵌入式处理器功能的Verilog源码及说明-FPGA with embedded ARM processor to achieve the functional descr iption of Verilog source code and
CPU_Architecture
- Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network pack
TMS320LF2407
- 第0章绪论.数字信号处理器(DSP)综述 第1章TMS320LF240X系列DSP概述 第2章系统配置和中断 第3章存储器及I/O空间 第4章时钟和低功耗模式 第5章数字输入输出 第6章事件管理器（EV) 第7章模数转换（ADC)模块 第8章串行通信接口（SCI) 第9章串行外设接口SPI 第10章CAN控制器模块 第11章看门狗（WD)定时器 第12章DSP开发工具与开发环境 第13
spru671
- OMAP5910 Dual-Core Processor MPU Subsystems Reference Guide
KM
- vhdl code 16 bit processor
multiprocessor
- multi processor scheduling with genetic algorithm
mips
- 使用verilog設計的MIPS處理器，mips處理機的模擬且可合成驗証-MIPS processor using the verilog design, mips processor synthesis of analog and can be verified
nnARM_tb01_09_02
- arm processor verilog code
nnARM_tb01_07_19
- verilog code for ope processor
mnl_nios_programmers32
- nios处理器的介绍以及汇编代码的说明，altera公司的官方文件-introduction of nios processor & descr iption of assembly code
4by4
- 4输入，4输出，clos网络所用，有利于连接处理器和处理器，处理器和存储器传输数据。-4 inputs, 4 outputs, clos network use is conducive to connecting the processor and processor, processor and memory to transfer data.
mlite.tar
- 很强大的mips处理器，用verilog实现的-A very strong mips processor implemented using verilog
m1_core.tar
- 一个小巧的mips处理器，verilog写的，大家可以-A small mips processor, verilog written, we can see
mips789.tar
- 一个功能很完善，很强大的mips处理器，verilog编写的-A feature is perfect, very strong mips processor, verilog prepared
processor
- verilog program for alu
MANIK
- MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed below. Features Hardware Features • Data Path Width 32 bits, with Four stage pipeline. • Mixed 16/32 bit instruc
GPU_in_VHDL
- 这是一篇关于在可编程逻辑器件（CPLD）上实现一个8 比特的图形处理器GPU的报告-This report is about how to achieve an 8-bit graphics processor GPU on the programmable logic device (CPLD).
vliw
- vliw processor core vhdl files compiled by myself partly and through the help of net resources.
Processor_alu
- this Code is in verilog HDL. This Code is for piplined processor with 4 opcode. this will work in three cycle latch, decode and exicute.. test bench for xilinx ise is laos given
P7_Procesador
- SIMPLE PROCESSOR CODE