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RISC_Core.ZIP
- 这是一篇关于8位RISC CPU设计的文章，其中包含了用Verilog语言编写的CPU内核程序-This is an 8-bit RISC CPU on the design of the article, which includes using the Verilog language CPU core procedures
32-bit_RISC_IP_Core
- 32位RISC单片机verilog源码内包含说明文档经过他人测试通过-32-bit RISC single-chip Verilog source code contains documentation of others after the test
minirisc.tar
- verilog code .descrip the risc cpu.download from opencores.org-verilog code. descrip the risc cpu.download from opencores.org
simplesim-2.0.tar
- RISC处理器仿真分析程序。可以用于研究通用RISC处理器的指令和架构设计。在linux下编译，但也可在VC++中编译-RISC processor simulation analysis procedures. Can be used to study the generic RISC processor instructions and architecture design. In the compiler under linux
8bitRISCmicroprocessor
- this a 8-bit risc micro process,Th eM C Ud esignedis c ompatiblew ith PIC16C57 o microchip Technology Inc.in the instruction system
alu
- 16位RISC CPU的ALU，使用VHDL编写-16-bit RISC CPU
mtk_u9
- this a metelk company 1379 risc file,it is very good file.
RiscCPU8
- 可综合的VerilogHDL设计实例: ---简化的RISC 8位CPU设计简介--- -VerilogHDL be integrated design example:--- simplified RISC 8 bit CPU design Introduction---
ARelativelySimpleRISCCPU
- A Relatively Simple RISC CPU 设计源码并附详细的说明文档。可以ModelSim进行仿真，并可以用synplify进行综合。-A Relatively Simple RISC CPU design source with detailed documentation. ModelSim simulation can be carried out, and they can Synplify synthesis.
ATmega128(L)_cn
- 高性能、低功耗的 AVR® 8 位微处理器 • 先进的 RISC 结构 – 133 条指令 – 大多数可以在一个时钟周期内完成 – 32 x 8 通用工作寄存器 + 外设控制寄存器 – 全静态工作 – 工作于16 MHz 时性能高达16 MIPS-High-performance, low power AVR ? 8-bit microcontroller
risc_cpu
- 8位risc cpu的编写，使用quartus软件对其进行写入，里面内置乘法器、除法器等模块-8-bit risc cpu the preparation, use the Quartus software to write, which built-in multiplier, divider modules
RISC_Core
- 这是用VerilogHDL描述的一个8位精简指令集处理器，包含完整代码，各种文档，以及测试环境。-This is described in VerilogHDL with an 8-bit RISC processor, including the integrity of the code, a variety of documents, as well as the test environment.
RiscCpu
- 4位RISC指令CPU源码,需要的朋友可以看看!-4 RISC instructions CPU source, can look at the Friend in need!
RISC_CPU
- RISC CPU IP CORE 可以用于直接的工程开发应用 有详细的说明书-RISC CPU IP CORE can be used to direct the development and application of the project has a detailed brochure
verilog_risc
- RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优化可实现高效的流水线操作。 RISC 中的数据线为16位。 在数据存储器中的0到15的位置放置16个随机数，求16个数的和，放在数据存储器的16、17的位置，高位在前 对这16个数进行排序，从大到小放置在18到33的位置 求出前16个数的平均数，放在34的位置 基本指令有NOP, ADD, SUB, AND, RD, WR, BR
RiscCpu
- Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design m
32bit_RISC_CPU
- 32 risc cpu的参考设计，内涵完整的testbench-32 risc cpu s reference design, the connotation of complete Testbench
ThreadX_ARM
- ThreadX Library for ARM RISC microprocessor. ThreadX is a high performance RTOS that is wildly used in industrail world-wide.
RISC8.ZIP
- verilog RISC8 cpu CORE 8位RISC CPU 内核源码（VERILOG 版）-verilogRISC8 cpu CORE8-bit RISC CPU core source (VERILOG version)
dkljfkjls
- RISC处理器设计.ppt RISC处理器设计.ppt RISC处理器设计.ppt-RISC processor design. PptRISC processor design. PptRISC processor design. PptRISC processor design. PptRISC processor design. Ppt