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california_university_8051_cPPmodel
- 加州大学研究生做的8051 C++模型，用于8051cpu的仿真验证。可作为的systemverilog中调用的golden model使用-University of California graduate student doing 8051 C++ model for the simulation 8051cpu. Golden model can be invoked as a systemverilog use
Blackjack
- Blackjack program VHDL program SystemVerilog
John-Havlicek-Presentation
- FSL SystemVerilog Requirements Requirements on basic constructs and types Requirements on assertions Requirements on external capabilities Requirements on hierarchy Requi
sv-reference-doc
- systemverilog入门 用于IC验证-for test
SystemC
- System C FPGA仿真软件,与SystemVerilog配合-System C for FPGA
systemverilog
- 是关于System Verilog的课件，简要介绍了了System Verilog的用法，主要介绍进行可仿真和可综合的硬件设计，作为Verilog的扩展，在抽象设计、测试平台和基于C语言的应用程序设计接口有重大改进。-About System Verilog courseware, brief introduction of System Verilog usage introduces conduct can be integrate
viterbi-systemverilog
- viterbi decoder (2,1,7)(133,171)-viterbi decoder (2,1,7)
AES
- AES代码 加解密代码 systemverilog编程-AES code
SV_Guidelines
- SystemVerilog Coding Guidlines
ahb_master_agent
- Ahb master agent in systemverilog
ahb_slave_driver
- Slave driver in systemverilog for AHB
eth_mac_frame
- Class file to handle creation of Ethernet fr a me content SystemVerilog Language
UVM_Golden_Reference_Guide
- The UVM Golden Reference Guide is a compact reference guide to the Universal Verification Methodology for SystemVerilog. it offers answers to the questions most often asked during the practical application of UVM i
udp_send1
- 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk
UVM_Class_Reference_Manual_1.2
- The UVM Class Library provides the building blocks needed to quickly develop wellconstructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed ref
MEMORY
- Systemverilog interface for memory model
SystemVerilog-for-Verification
- system Verilog for verification
Modelsim-System-verilog-calls-DPI
- 本文给出了在Modelsim开发环境下，如何在systemverilog中利用DPI调用C函数的具体方法。-This paper gives a specific way to call C functions in DPPHs in systemverilog in Modelsim development environment
2013-SNUG-SV_Synthesizable-SystemVerilog_paper.zi
- cummins snug paper systemverilog constructs
uart2bus_testbench_latest.tar
- uart2bus_testbench,uart测试平台，主要运用uvm验证方法学，对uart接口、systemverilog和uvm等ic开发和验证有一个初步了解和掌握。-Uart2bus_testbench, uart test platform, the main use of uvm validation methodology, uart interface, systemverilog and uvm ic developme