搜索资源列表
verilog_testbench_preliminary
- verilog testbench preliminary，很有用的-verilog testbench preliminary, very useful
alu1
- alu,原程序及testbench,供初学者参考-alu, the original procedures and testbench and reference for beginners
register19
- register,原程序及testbench,供初学者参考-register, the original procedures and testbench and reference for beginners
timing19
- timing,原程序及testbench,供初学者参考-timing, the original procedures and testbench and reference for beginners
cfft
- 参数化FFT源代码，点数和位宽可变，内附testbench和说明文档-parameters of the source code FFT, counting and variable bit-enclosing testbench and documentation
RISCMCU
- riscMCU的VHDL实现，内附有modelsim仿真testbench和文档说明-riscMCU VHDL, modelsim containing a simulation testbench and documentation shows
oc8051
- 8051的verilog实现，内附testbench,c语言调试程序-8051 verilog achieve, enclosing testbench, c language debugging procedures
FIFO_v
- FIFO的verilog实现，内附testbench和文档说明-FIFO verilog achieve, enclosing testbench and documentation shows
TestBench_writing
- testbench书写规范格式的ppt教程
systemverilog
- systemverilog是新出现的一种高级硬件描述和验证语言，这里给出了一些书和文章还有使用vmm方法开发testbench的例子
s_fifo
- 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared regi
fifo
- 一个同步FIFO，包括testbench，-A synchronous FIFO, including the testbench,
i2c
- I2C controller的源码，包括TESTBENCH在内，里面包含有EEPROM的behaving model，前些日子在本站下了一个EEPROM的behaving model，发现可能只是作者的初版，里面错误比较多，因此上传一个能编译拿过来就能用的环境。-I2C controller source code, including the Testbench included, which contains EEPROM
testbench
- 一个自己编写的全数字锁相环及其测试向量，比较简单但功能基本达到。-I have written an all-digital phase-locked loop and its test vectors, relatively simple to achieve but the basic function.
core_arm.tar
- vhdl的arm核 包含testbench-VHDL Testbench contain the nuclear arm
guiden-to-write-efficient-testbench
- 这是一个xilinx公司发布的写testbenth的入门向导，指导我们快速高效的写自己的testbenth，从而改进我们的仿真效果。 -This is a Xilinx Inc. released testbenth write entry wizard, guiding us to quickly and efficiently write their own testbenth, in order to improve our si
testbench
- 32位除法器的测试程序， 由随机向量产生函数产生一组随机数 来验证计算书否正确-32 divider test procedures, by the random vector generated a set of functions to generate random numbers to verify whether the correct calculation of the book
ddstest
- 实现dds的testbench，很有帮助-Dds to achieve the testbench, helpful
counter
- VHDL计数器的TestBench，适合初学者-VHDL counter TestBench, suitable for beginners
Verifying_the_Quality_of_Your_Testbench_with_code_
- Testbenches have become an integral part of the design process, enabling you to verify that your HDL model is sufficiently tested before implementing your design and helping you automate the design verification proce