搜索资源列表
dac
- DAC converter design with Verilog code and testbench
I2C_HDL
- I2C bus HDL source and testbench
i2c.tar
- i2c总线控制器ipcore，包含testbench-i2c bus controller ipcore, contains Testbench
WritingTestbenches
- 编写testbench的超好教程，网上这种资料比较少。(Kluwer) Writing Testbenches--Functional Verification of HDL Models.pdf-Testbench prepared super good tutorials, on-line this information is relatively small. (Kluwer) Writing Testbenches Funct
test_bench_top
- 用于AES加密的testbench。产生激励-AES encryption for testbench. Incentive
tb_w
- 简单的testbench制作方法，对初学者有点帮助-Testbench simple manufacturing method, for beginners a little help
trueif
- 一个超前进位加法器（及其testbench) .v文件-A CLA (and its testbench). V file
crc16_ccitt
- crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a verilog module of byte paralle crc. CRC16_D8_m_tb.v is the testbench file of above module. -crc_table.c is for reset se
textio
- vhdl testbench的编写，textio的编写是一个难点，也是一个重点，而这是本人搜集的多篇关于textio的文章，同时附有简单注释!-vhdl testbench preparation, textio the preparation is a difficult, but also a focus, and this is my collection of articles on textio the article, at
testbench
- IC验证，一本不可多得的好书，讲的非常全面。-IC verification, a rare book, talking about very comprehensive.
MinWinsockSpi
- verilog ADPLL file with testbench
SPI_FireWall
- verilog spi file with testbench
wince+spi
- verilog vcspi file with testbench
UART
- 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
RAMtestbench
- 双口Ram的VHDL Testbench-Dual-Port Ram s VHDL Testbench
risc
- 嵌入式risc处理器源码，包含设计文档，原理图，testbench，及外围接口，使用verilog实现。-Source embedded RISC processors, including design documents, schematics, testbench, and peripheral interfaces, the use of Verilog to achieve.
adder4
- 是用verilog写得加法器以及计数器里面有测试文件（testbench），对于初学者来说这个可以用来参考下-Is written in Verilog adder and counter inside a test file (testbench), for beginners this can be used to reference the next
custom_cordic
- verilog编程开发的cordic例程，计算SIN,COS功能与计算幅值角度功能可设定，运算宽度可设定，并有完善的TESTBENCH。-Verilog programming developed CORDIC routines to calculate SIN, COS function and calculating the amplitude of the perspective of function can be set, c
8051_IP_Verilog
- 8051单片机源码verilog版本 包括rtl， testbench， synthesis -Verilog source code version of 8051, including rtl, testbench, synthesis
Am29lv160d
- 在逻辑的系统仿真中使用的FLASH模型（AMD的Am29lv160d），包括VHDL代码文件和verilog代码文件和testbench，并且有相应的pdf说明文档。-In the logic system used in FLASH simulation model (AMD s Am29lv160d), including VHDL and Verilog source code files of documents and tes