搜索资源列表
XiaYuWen_8_RISC_CPU
- 夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的neged
testbench
- ddr sdram controller datd module source code
spi2-testbench
- test bench for spi communication
testbenchcpu8080
- this is code testbench cpu -this is code testbench cpu 8080
vrt
- Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。-Variable Reduction Testbench is a MATLAB module that allows the application of several methods for variable reduction based on correlation analysis
hssdrc_latest.tar
- HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in M
pcie_vera_tb_latest.tar
- FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC gener
generic_testbench
- VHDL中关于generic的用法，及其testbench，可以使用Modelsim仿真查看其功能-the usage of generic,a testbench file is given, we can use it to simulate the generic s function
vhdltestbench
- testbench,VHDL的，适合初学者使用-testbench
testbench
- 关于如何写Verilog测试台的文档，对于测试程序很有帮助噢-On how to write Verilog test documents, test procedures for helpful Oh
UARTtransmitter
- UART Transmitter. VHDL code and its testbench.
shiftregister
- Shift Register. VHDL code and its testbench.
register
- it is source code of 32 bit register and testbench for tht register written in verilog.
20081129464173846
- 介绍Verilog HDL, 内容包括： – Verilog应用 – Verilog语言的构成元素 – 结构级描述及仿真 – 行为级描述及仿真 – 延时的特点及说明 – 介绍Verilog testbench • 激励和控制和描述 • 结果的产生及验证 – 任务task及函数function – 用户定义的基本单元(primitive) – 可综合的Verilog描述风格-
cascaded_adder
- implementation of cascade adder with verilog plus testbench
contador_n_bits
- n-bits counter vhdl with testbench. contador de nbits en vhdl con simulacion.
BMD.RAR
- xilinx BMD ver 10 pciexpress testbench for master design
ascfifotestbench
- 自写异步 fifo TESTBench 该fifo对初学者很有帮助！-Since the write fifo TESTBench asynchronous fifo very helpful for beginners!
rom_table
- rom vector table vhdl and Testbench
fifo
- 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave