搜索资源列表
61EDA_D721
- 8*8乘法器设计,和大家共享,互相学习,共同进步-8* 8 multiplier design, and for all to share and learn from each other and progress together
add
- 流水线乘法器与加法器 开发环境:Modelsim(verilog hdl)-Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
mul
- 加法器树乘法器结合了移位相加乘法器和查找表乘法器的优点。它使用的加法器数目等于操作数位数减 1 ,加法器精度为操作数位数的2倍,需要的与门数等于操作数的平方。 因此 8 位乘法器需要7个15位加法器和64个与门-Adder tree multiplier multiplier combination of shift and add multiplier advantage of look-up table. It uses the a
multiplier
- 乘法器在FPGA中的VHDL代码实现教程-Multipliers in the FPGA code in VHDL Tutorial
mul24x24
- 24位x24位的乘法器 十分详细24位x24位的乘法器24位 x24位的乘法器24位 x24位的乘法器24位 x24位的乘法器24位x24位的乘法器-24-bit x24-bit multiplier very detailed 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of
16bit_multiply
- 一个16位并行乘法器, 已经进过功能验证, 可以用于综合。 -a 16bit parallel multiply after verification, can be used to synthesis
mux4
- 四位乘法器的VHDL语言设计,并有原理图的描述-4 Multiplier VHDL language design, and schematic descr iption of
multiplier
- 该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。 其乘法原理是:乘法通过逐项移位相加原理来实现,从被乘数的最低位开始,若为1,则乘数左移后与上一次的和相加;若为0,左移后以全零相加,直至被乘数的最高位。-The multiplier is 8-bit adder consisting of time-series design to the 8-bit multiplier. The multiplication princ
VHDL
- VHDL对各种电路的基本实现,包括乘法器,触发器,加减法器等-VHDL for the basic realization of the various circuits, including multipliers, flip-flops, and other instruments used in addition and subtraction
verilog
- verilog语言例题集锦 包含加法器,乘法器,串并转换器等verilog源代码-Example Collection contains verilog language adder, multiplier, and converters, such as string verilog source code
Multiple
- 高效的乘法器设计,既节约面积,又提高性能,同时减少开发周期-Efficient multiplier design, both to save space and improve performance while reducing the development cycle
qfq
- 移位相加乘法器设计。附有工程实例及ppt说明。-Add multiplier design shift. Ppt with example and descr iption.
FPGA
- 基于FPGA数字乘法器的设计:数字乘法嚣是目前数字信号处理中运用最广泛的执行部件之一,本文设计了三种基于FPGA 的数字乘法器.分别是移位相加乘法嚣、加法器树乘法器和移位相加一加法嚣树混合乘法器。通过对三种方案的仿真综合以厦速度和面积的比较指出了混合乘法器是其中最佳的设计方案-FPGA-based digital multiplier design: the number of multiplicative noise is the u
multiprocessor
- 简单的乘法器的内核测试,已经验证通过,VLOGER编写-The core of a simple multiplier tests have verified through, VLOGER prepared
mutiplier
- 用VHDL语言仿真乘法器设计, 经过modelsim仿真, synplify综合,并下载进FPGA验证-Multiplier design using VHDL, simulation, after modelsim simulation, synplify synthesis, and downloaded into a FPGA verification
multiplexer
- 几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
multi
- 8位乘法器,Quters编译环境VHDL代码-pluter VHDL Quters
Lab4
- 实现原码一位乘法器,但必须位数相同才行。-hdbadbkwdk
16bit_mult
- 16位的无符号数乘法器,自己写的,经得起验证,注释很详细-16-bit unsigned multiplier, its own written
maths
- multiplux,8*8的单片机乘法器-for the microcontroller