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rc6_avr
- AVR单片机的优化RC6 加密算法（速度快，其优化思想绝对值得学习） 在有128bytes RAM 的AVR单片机上执行 rc6 16/10/8(16 bit/10 rounds/8 bytes keys) * 对多数代码进行了 C 语言优化，对数据相关循环移位，模乘等用ASM优化 * 在4MHz无乘法器的AVR上得到平均 1172 Bytes/s的加解密速度。 * 编译器: AVR-G-AVR optimiza
booth_mul
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols / unsigned multiplication of the number of binary multiplier
statemachine_mult
- veilog实现的状态机乘法器.可以参考-veilog achieve the state machine multiplier. Can reference
Verilog_Development_Board_Sources
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Develo
comp_arith
- cpu设计中关于加法器，乘法器，除法器设计的ppt，希望对硬件学习的人有帮助-cpu design on the adder, multiplier, divider design ppt, want to learn hardware help
VHDL
- 本代码为用VHDL语言设计实现加法器、减法器、乘法器，并提供了模块图，进行了波形仿真。-This code is for the use of VHDL Language Design and Implementation of adder, subtracter, multiplier, and provides a block diagram carried out a wave simulation.
jianyijisuanqiVHDL
- 用VHDL写的简易计算器，包括加减乘除，除法器用加法器和乘法器组成-Write simple calculator with VHDL, division, including add, subtract, multiply and divide adder on time-multiplier and used
16bit-multiplier
- 实现verilog16位乘法器，verilog新手(achieve 16-bit multiplier)
booth
- 基于booth算法的16位乘法器，通过减少部分积的运算次数提升速度。(The 16 bit multiplier based on the Booth algorithm improves the speed by reducing the number of arithmetic times of the partial product.)
17
- CSD实现一个乘法器，是一个十一位乘以十七的乘法器，可用于滤波器的相关乘法器设计。(CSD implements a multiplie)
流水线乘法累加器设计
- 调用寄存器LPM,流水线加法器LPM,流水线乘法器LPM等模块实现一个8位流水线乘法累加器。(Call a register LPM, pipelined adder LPM, pipeline multiplier LPM and other modules to achieve a 8 bit pipelined multiplication accumulator.)
16 bit signed number multiplier
- 16位有符号数乘法器，使用Booth编码和华莱士树，提供程序源文件和测试文件(The 16 bit signed multiplier uses Booth encoding and Wallace tree to provide source files and test files.)
mux16
- 基于quartus的FPGA乘法器Verilog程序(FPGA multiplier program based on quartus)
float_mult32x32.v
- verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock
multiplication
- 在FPGA里面实现了多位乘法器的功能，并用modelsim进行了仿真，还对该乘法器进行了优化(The function of multi-bit multiplier is realized in the FPGA, and it is simulated with modelsim, and the multiplier is optimized)
fpmul
- Verilog语言编写的单精度浮点数乘法器(The Verilog language of single precision floating point multiplie)
multi
- 基于Verilog HDL 的乘法器，可以实现一些功能的计算(Multiplier based on Verilog HDL)
multiplier
- Booth乘法器是属于位操作乘法器，采用流水线结构实现(The Booth multiplier is a bit-operated multiplier that is implemented in a pipeline structure.)