搜索资源列表
xulie
- 基于FPGA的任意序列检测器，其中有序列发生器-FPGA-based detection of any sequence, including sequence generator
m_ca7
- verilog编写的基于CA算法的m序列发生器，其中验证了多种CA系数来实现m序列。-CA-based algorithm written in verilog m-sequence generator, which verify the CA factor to achieve a variety of m-sequence.
VHDL-source-code
- 一些有用的VHDL代码 包括伪随机序列发生器等-VHDL code, including some useful pseudo-random sequence generator, etc.
matlab
- 基于matlab的直流序列发生器，包括m序列的产生，扩频等功能-m seguence frequency spread DSSS
vhdl--eda
- m 序列发生器 计数器 七段数码管显示 bcd 十六进制转换-failed to translate
F2812_AD01
- F2812 ADC01 （CCS3.3开发环境下）软件置位启动AD转换，实现ADC模块16路通道的采样。序列发生器SEQ1和SEQ2级联成一个16通道的序列发生器，采样模式采用顺序采样。-F2812 ADC01 software is set to start AD conversion, the ADC module 16-channel sampling. Sequencer SEQ1 and SEQ2 cascade into a
F2812_AD02
- F2812 AD02 （CCS3.3开发环境下）T1周期中断启动ADC，实现ADC模块16路通道的采样.AD采样频率为10K，序列发生器SEQ1和SEQ2级联成一个16通道的序列发生器，采样模式采用并发采样。利用通用定时器T1的周期中断来触发AD转换。-F2812 AD02 .T1 cycle interrupt start ADC, the ADC module 16-channel sampling. AD sampling rat
AD01
- DSP2812的AD转换程序，序列发生器SEQ1和SEQ2级联成一个16通道的序列发生器，采样模式采用顺序采样。AD采样的触发方式采用软件置位的方式。-DSP2812 AD conversion program, the sequence generator SEQ1 and SEQ2 cascades into a 16 channel sequence generator using sequential sampling, sam
ADSample
- dsp2812的AD采样程序,AD采样频率为10K，序列发生器SEQ1和SEQ2级联成一个16通道的序列发生器，采样模式采用顺序采样。利用通用定时器T1的周期中断事件来启动AD转换。-AD sampling program of DSP2812
sequential-detactor
- 本次例程包括七阶伪随机序列发生器、序列码检测器，奇偶校验器、CRC（循环冗余）校验器，并附有FPGA的代码和仿真。-The routines including seven order pseudo-random sequence generator, sequence yards detector, parity validator, CRC (cyclic redundancy) validator, and with FPGA c
mxulie_lfsr
- m序列发生器，使用移位寄存器生成，电子设计大赛使用过的-m sequence generator, using a shift register to generate, Electronic Design Contest used
2DPSK-linan
- 全数字2DPSK调制解调系统，为VHDL语言。包括512分频器，M序列发生器等。整个过程完成2DPSK的调制与解调。-The full the digital 2DPSK modem system for the VHDL language. Including the 512 divider, the M-sequence generator. The whole process is completed 2DPSK modulati
ADC
- 2812中的adc源文件 序列发生器SEQ1和SEQ2级联成一个16通道的序列发生器，采样模式采用顺序采样-the adc source file in the dsp2812, SEQ1 and SEQ2 cascade into a SEQ which have 16 paths, it adopt seqencetial sampling
Based-on-the-Matlab
- 基于Matlab的m序列发生器的设计（内附matlab程序）-Based on the Matlab m sequence generator design (enclosed Matlab)
m
- 很好的几个M序列发生器代码 matlab平台 参考价值很大 直接用-The direct use of good reference value of several M-sequence generator code matlab platform
pseudo-random-sequence-generator-
- 利用FPGA编程--- -实现“伪随机序列发生器设计”-FPGA programming------- pseudo-random sequence generator design
xulie_100111
- 用verilog语言编写的并且仿真通过的100111序列发生器的工程文件夹-the generator of 100111
Pseudo-random-sequence-generator
- 通过MATLAB的SIMULINK模型设计，实现伪随机数的序列发生器，并通过DSP BUILDER中的SIGNAL COMPILER转换成QuartusII工程，并实现硬件的下载。-Through the MATLAB SIMULINK model design, realization of pseudo random sequence generator, and through the DSP BUILDER of SIGNAL
wei_xulie
- 为序列发生器，数字系统传输性能分析设计，做眼图测试用-Sequence generator, digital transmission performance of system analysis and design, make eye test
m_seq
- 用VHDL代码编写的m序列发生器，包含发生器和测试用例模块-M sequence generator written in VHDL code, including the generator and the test case module