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gf
- 在CCS6.0平台上用C语言编写的基于DSP2812的配合改进型H5拓扑结构逆变器的控制程序，控制方式为带锁相环的对称规则法SPWM输出加50Hz频率相位可调方波输出-In the CCS6.0 platform using C language written based on DSP2812 improved type H5 topology inverter control procedures, control mode wit
YD
- 运用qurtus9.0进行全数字锁相环的制作，内含有各个模块及程序注释。-Of all digital phase-locked loop with qurtus9.0 production, contains various modules and application notes
dianyaqiankui
- 电流控制，利用电压前馈补偿控制，有锁相环，单相并网控制系统。亲自测试，修改，可以仿真。希望对大家学习并网有用。-Current control, the use of voltage feedforward compensation control, phase-locked loop, and single-phase network control system.
SPLL_1ph_digital_2
- 单相锁相环simulink仿真，用于并网逆变等，大部分不是自带模型，根据相关资料和离散方程搭建，比较实用。基于matlab2014b-Single-phase locked loop simulink simulation for grid-connected inverter, etc., most are not built model, according to the relevant data structures and d
PLL.plecs
- PLECS是一个用于电路和控制结合的多功能仿真软件，尤其适用于电力电子和传动系统。这个PLECS模块是一个锁相环（这个软件没有自带锁相环），这个锁相环是照着MATLAB底层文件搭建的-PLECS is a versatile simulation software for circuit and control, especially for power electronics and transmission system. This
pllmb15a02yuanliverygood
- PLL锁相环合成器MB15A02内部技术资料，好好学习，很快就可搞定PLL的编程工作。-mb15a02 pll program,student PLL good program file.
lab4-timer1_LED
- 初始化系统控制： 锁相环，看门狗，使外设时钟 这个例子是在dsp2833x_sysctrl发现C文件。-Initialize System Control: PLL, WatchDog, enable Peripheral Clocks This example function is found in the DSP2833x_SysCtrl.c file.
PLL_DOCUMENT_MC145151-2
- 锁相环MC145151-2集成电路完整资料,对研究PLL很有帮助,好好理解,事倍功半.-MC145151 IC DATASHEET ,PLL VCO VERY GOOD.
c8051f330_mix_20160616
- 单片机C8051F310控制锁相环（ADF4002）,初始化和控制锁相环-C8051F310 MCU control phase-locked loop (ADF4002)
c51_pll
- C51IC,锁相环MC145151-2集成电路完整资料,对研究PLL编程很有帮助,好好理解,事倍功半.-c51ic,pll ic.
ADF4360-7
- 此程序是c8051f330单片机控制adf4360-7锁相环输出固定点频程序 -This program is controlled by MCU This program is c8051f330 single-chip microcomputer control adf4360-7 phase-locked loop frequency output protection program
SPLL
- 单同步坐标系锁相环，适用于电网电压平衡时的相位，频率及其幅值的检测-Single phase-locked loop synchronous coordinate system for the grid voltage balancing phase, frequency and amplitude detection
inverters-without-phase-lock-loop
- 不平衡电网下无锁相环三相并网逆变器控制策略-inverters without phase-lock loop
06_pll_test
- PLL实现，在xilinx spartan 6的参考时钟50MHz上实现不同频率的锁相环程序-PLL implementation, in the Spartan Xilinx 6 reference clock 50MHz on the realization of different frequencies of the phase-locked loop program
pll_SOGI
- 基于SOGI（2阶广义积分器）的单相锁相环simulink仿真，参考《光伏与风力发电系统并网变换器》周克亮译 71页-Based on SOGI (2-order generalized integrator) single-phase phase-locked loop simulink simulation, refer to Grid Converters for Photovoltaic and Wind Power Syst
IIC
- 飞思卡尔单片机IIC总线编程，控制时钟、锁相环设置IIC总线频率，数据收发验证。-iic bus programming source code, including initialization, data sent and received.
pll
- 基于PSIM的锁相环。可以放在任何PSIM的模型，例如三相并网和单相的也可以的-Phase Locked Loop Based on. Can be placed in any PSIM model, such as three-phase and single phase can also be
PLL
- 锁相环仿真，有三个独立的文件，输入信号都是FM信号-PLL Simulation
hmc833-for-msp430f14X
- 使用openmode控制锁相环芯片HMC833，MSP430F14x系列单片机-control hmc833 in openmode,for msp430f14x mcus
pll_matlab
- 采用二阶换仿真锁相环的matlab代码，仿真结果ok，频偏200kHz.-it is used to simulate the PLL system.