搜索资源列表
altera+dpd
- 数字预失真在通信领域内IP核的开发文档,包括数学表达式及硬件框图-Digital Predistortion in the field of IP communications in the development of nuclear documents, including mathematical expression and hardware block diagram
jurbojtag
- turbo jtag CPLD source code use altera EPM7128S -turbo jtag CPLD source code use altera EPM7 128S
ref-ddr-sdram-vhdl
- 本程序是DDR SDRAM控制器的VHDL程序,由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Gerbers_DSP2_REV_C
- 记算功耗与ALTERA 的高端器件的设计验证-operator credited with the power of Altera's high-end device design certification
bingxingtongxin
- 介绍了用ALTERA公司MAX7000系列CPLD芯片实现单片机与PC104ISA总线接口之间的关行通信。给出了系统设计方法及程序源代码。 -introduces the MAX7000 Altera Corporation Series CPLD The position with SCM 04ISA bus interface between the telecommunications firms. Gives the sy
verilog-som
- 拿verilog编写的som(自适应神经网络算法),用于障碍物检测,基于FPGA可综合实验,已经在altera的cylcone上实现-Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone
Project1-DDS
- 直接频率和成DDS,可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
SIN_fashengqi
- 2006altera大赛-基于软核Nios的宽谱正弦信号发生器设计:摘要:本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA公司的 Cyclone 系列 FPGA 为数字平台,将微处理器、总线、数字频率合成器、存储器和 I/O 接口等硬件设备集中在一片 FPGA 上,利用直接数字频率合成技术、数字调制技术实现所要求波形的产生,用 FPGA 中的 ROM 储存 DDS 所需的波形表,充分利用片上资源,提
CPLDxiaoche
- 智能机器小车主要完成寻迹功能,由机械结构和控制单元两个部分组成。机械结构是一个由底盘、前后辅助轮、控制板支架、传感器支架、左右驱动轮、步进电机等组成。控制单元部分主要由主要包含传感器及其调理电路、步进电机及驱动电路、控制器三个部分。本设计的核心为控制器部分,采用Altera MAX7000S系列的EPM7064LC84-15作主控芯片。CPLD芯片的设计主要在MAX+plusⅡ10.0环境下利用VHDL语言编程实现。驱动步进电机电路主要
QuartusII_Flow
- altera公司关于QuartusII操作平台的培训教案,对初学者来说可以受益匪浅-altera QuartusII companies operating platform on the training lesson plans, the newcomer could benefit greatly
pwm_source
- ALTERA PWM電路 這是一個ALTERA的PWM電路,可以整合到NIOSII IDE中,來完成一個PWM的系統。-Altera PWM circuit Altera This is a PWM circuit, NIOSII can be integrated into the IDE, to complete a PWM system.
adda_spi
- 这个源码是用altera公司的开发工具NIOS II IDE开发的基于软核处理器的AD、DA控制程序,通过spi 核控制AD、DA的时序,实现正弦波发送和接收-this source is altera company development tools NIOS II IDE- based soft-core Office JIMMY of AD and DA control procedures, spi nuclear contr
hello_world_0
- 此源码是用altera公司的nios II IDE开发的,基于DE2核心板的SD卡播放wav格式音频文件的程序-This source is altera s nios II IDE development, based on the core DE2 board SD card playback wav format audio files
8051_nios_vhdl
- 8051 MCU在nois平台上的实现代码(VHDL),出自Altera公司,经过严格测试核验证-nois 8051 MCU platform in the realization of code (VHDL) from Altera Corporation, after strict verification of nuclear test
8051_nios_doc
- 8051 MCU在nois平台上实现的说明文档,讲解非常详细,对于设计很有帮助,出自Altera公司。-nois 8051 MCU platform in the realization of documentation to explain in great detail, useful for the design, from Altera Corporation.
altera_avalon_pwm
- Avalon altera pwm generator. Directly use in SOPC.
multi_cpu_2c35
- altera的fpga设计,包含硬件原理图和软件例程,用nios工具等-altera the FPGA design, contains hardware schematics and software routines, using tools such as Nios
AlteraQuartusII6.0crack
- Altera Quartus II 6.0 破解文件-Altera Quartus II 6.0 crack documents
16450
- ALTERA的16450IPCORE能得到源代码的适合古老的芯片可以作为学习参考-the source code will be suitable for the old chip can be used as Learning reference
8237
- ALTERA 8237IPCORE 可以得到源代码的适合初学者学习-Altera 8237IPCORE be source code for beginners learning