资源列表
[VHDL编程] vhdl-primer-bhaskar
说明：It s a fundamental book on VHDL primer by Bhaskar...good for final year bachelor s students-It s a fundamental book on VHDL primer by Bhaskar...good for final year bachelor s students...<aditya> 在 2026-01-02 上传 | 大小：1.07mb | 下载：0
[VHDL编程] datacompresstion12
说明：jpeg velrilog code its a very good project for mainproject<rama krishna raju> 在 2026-01-02 上传 | 大小：659kb | 下载：0
[VHDL编程] fixed_package
说明：Hi useful exponential code in vhdl<prakash> 在 2026-01-02 上传 | 大小：24kb | 下载：0
[VHDL编程] new_PCI2009-123456ppp
说明：FPGA和PCI9054做的图像采集卡VC测试程序源码，有三种显示模式。-FPGA and PCI9054 VC image capture card to do the test program source code, there are three display modes.<yup> 在 2026-01-02 上传 | 大小：8.7mb | 下载：0
[VHDL编程] hw1
说明：Using the schematic Design Entry Method, design a logic circuit that has two 2-bit inputs X and Y, a 1-bit input CinOrBin, and a 1-bit control input SubAddn. When the control input SubAddn is ‘0’, the logic circuit behaves as a 2-bit adder ( X + Y +<vinay> 在 2026-01-02 上传 | 大小：357kb | 下载：0
[VHDL编程] hw2
说明：Using the VHDL Entry Method, design a logic circuit that behaves a 2-bit adder ( X + Y + CinOrBin ) with carry-in when the control input SubAddn is ‘0’ and behaves as a 2-bit subtracter ( X – Y – CinOrBin ) with borrow-in when the control input SubAd<vinay> 在 2026-01-02 上传 | 大小：613kb | 下载：0
[VHDL编程] hw3
说明：Write VHDL codes to model an 8-bit counter that counts every second. It counts from your last two digits of your student ID to your next two digits of your student ID. If the last two digits are greater than the next two digits, the counters counts d<vinay> 在 2026-01-02 上传 | 大小：344kb | 下载：0
[VHDL编程] hw5
说明：Design a 2-digit stopwatch that ticks every second. A switch is used to start and stop the time. When the switch is pushed, the time will start and when it is pushed again, the time will stop. In order for the switch to work properly, the switch must<vinay> 在 2026-01-02 上传 | 大小：1.31mb | 下载：0