资源列表
[VHDL编程] led_shizhong
说明:8位显示电子时钟,由7段数码管作为显示输出,带有调试调分调秒的按键功能-8-bit display digital clock, as the 7-segment display output, with sub-tone seconds debug button adjustment function<应斌斌> 在 2025-06-11 上传 | 大小:4kb | 下载:0
[VHDL编程] filter_stage1
说明:虑波器,可综合代码风格,易懂,好理解。十六位的-Recorder, which can be integrated code style, easy to understand, easy to understand<孟哲> 在 2025-06-11 上传 | 大小:2kb | 下载:0
[VHDL编程] filter_stage2
说明:滤波器,三十二位的,可综合代码,易懂好理解-Filter, Thirty, and can be integrated code, to understand better understanding<孟哲> 在 2025-06-11 上传 | 大小:2kb | 下载:0
[VHDL编程] filter_stage3
说明:滤波器,24位的,可综合代码,易懂好理解-Filters, 24-bit, and can be integrated code, to understand better understanding<孟哲> 在 2025-06-11 上传 | 大小:5kb | 下载:0
[VHDL编程] PracticalComputerVisionUsingC_diskette
说明:The diskettes associated with this book contain most of the code, organized by chapter, and a set of sample images. The code will compile using Borland Turbo-C on an IBM PC or compatible having a VGA card. The basic code for the Alpha<lover> 在 2025-06-11 上传 | 大小:490kb | 下载:0
[VHDL编程] an492_design_example
说明:it s a VHDL descr iption of FLASH memory<M4RKO> 在 2025-06-11 上传 | 大小:346kb | 下载:0
[VHDL编程] pll
说明:verilog硬件描述语言实现数字锁相环功能仿真,-Digital phase-locked loop using verilog<huashuyang> 在 2025-06-11 上传 | 大小:1kb | 下载:0