资源列表
[VHDL编程] shuzizhong
说明:数字钟,校时较分,显示,用元件例化写的vhdl文件,两个24进制,1个60进制计数器-Digital clock, when the school over the points, show cases with elements of writing vhdl file, two 24-band, a 60-ary counter<范天恩> 在 2024-05-03 上传 | 大小:467968 | 下载:0
[VHDL编程] jiaotongdeng
说明:理想状态的四路交通灯设计,用CPLD/FPGA驱动的,时间可以更改。-Ideal state of four traffic lights design, CPLD/FPGA-driven, time can be changed.<文辺> 在 2024-05-03 上传 | 大小:1024 | 下载:0
[VHDL编程] verilog_CPU
说明:用verilog写的RISC_CPU,描述文件很详尽,含有测试文件-Written by verilog RISC_CPU, very detailed descr iption of the file containing the test file<fyf> 在 2024-05-03 上传 | 大小:1012736 | 下载:0
[VHDL编程] des_vhdl_code
说明:decription aes using vhdl code<dani.hassoun> 在 2024-05-03 上传 | 大小:140288 | 下载:0
[VHDL编程] dec_aes
说明:decription aes vhdl code for fpga<dani.hassoun> 在 2024-05-03 上传 | 大小:12288 | 下载:0
[VHDL编程] 8051_cpu_verilog
说明:The 8051 microcontroller is member of MCS-51 family, originally designed in the 1980 s by Intel. The 8051 has gained great popularity since its introduction and is estimated it is used in a large percentage of all embedd<spetrel> 在 2024-05-03 上传 | 大小:87040 | 下载:0
[VHDL编程] C_ADDSUB_V1_0
说明:针对xilinx器件的重要库文件,能够加快基于xilinx器件的工程开发,提高系统的性能。-For important library xilinx devices, to accelerate project development based on xilinx devices to improve system performance.<spetrel> 在 2024-05-03 上传 | 大小:4096 | 下载:0