资源列表
[VHDL编程] WriteEfficientTestBenches
说明:TEST BENCHES FOR SIMULATION ARE VERY IMPORTANT FOR THE FINAL OUTCOME OF VERIFICATION DESIGN. WRITING EFFICIENT TEST BENCHES HELPS IN SIMULATING EFFICIENT DESIGNS<TAAL> 在 2025-06-19 上传 | 大小:193kb | 下载:0
[VHDL编程] counterFastSlow
说明:完整vhdl计数器,多种功能。 stop/ en/ fast/ slow/-Complete vhdl counter, a variety of functions. stop/en/fast/slow /<wwwss> 在 2025-06-19 上传 | 大小:1.21mb | 下载:0
[VHDL编程] vhd_SDH
说明:实现从连续传输的SDH字节流中找出帧头、提取F1字节,并按照64K速率分别串行输出F1码流及时钟,其中64K时钟要求基本均匀。文件包含报告文档-SDH transmission from a continuous stream of bytes to identify header, extract F1 bytes, respectively, in accordance with 64K-rate serial output bit stream and clock F1, of which<ljk05> 在 2025-06-19 上传 | 大小:69kb | 下载:0