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[VHDL编程] ee
说明：一个七段解码器模块，c2～c0是解码器的3个输入，当输入值不同时，输出不同的字符。如表中所示，当输入值为100～111时，输出空格，即数码管全暗。七段数码管的不同段位用数字0～6表示，注意七段数码管是共阳极的，即各管段输入低电平时，数码管亮；否则数码管暗。 -A seven-segment decoder module, c2 ~ c0 is a 3 input decoder, when the input value is not the same time, the output of d<潘小丽> 在 2025-06-08 上传 | 大小：2kb | 下载：0
[VHDL编程] SPIVerilogHDL
说明：SPI协议Verilog HDL程序包用Verilog语言实现fpga模拟实现spi协议功能-fpga-spi-verilog<zhn> 在 2025-06-08 上传 | 大小：83kb | 下载：0
[VHDL编程] Verilogexample
说明：verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci<vkiy> 在 2025-06-08 上传 | 大小：30kb | 下载：0
[VHDL编程] Verilog1C21B21A4_1237797332
说明：Verilog HDL Introduction 1.1 Verilog HDL Introduction 1.2 The basic concept of using the Verilog 1.3 Verilog HDL design concept of modular and hierarchical 1.4 Gate-level design module 1.5 data processing module design 1.6 Behavior Model<vkiy> 在 2025-06-08 上传 | 大小：4.19mb | 下载：0
[VHDL编程] VHDLtraining
说明：The basic concepts of VHDL language 1.1 Data types and data objects declared 1.2 VHDL descr iption of the syntax 1.3 Class design 1.4 functions, procedures and packages 1.5 Issues and discussion 1.6 References-The basic concepts of VHDL l<vkiy> 在 2025-06-08 上传 | 大小：1.5mb | 下载：0
[VHDL编程] XC4VLX60MB_Lab3_RS232_ISE91
说明：FPGA design, In addition to logic design, the future also can be SOC (System On Chip) approach to achieve a future A complete design system, so XC4VLX60 the board design includes RS232 and LCD surrounding the design, this experiment will Super te<vkiy> 在 2025-06-08 上传 | 大小：487kb | 下载：0
[VHDL编程] XC4VLX60MB_Lab5_PROM_ISE91
说明：XCVLXMB the board Xilinx SRAM_BASED FPGA design is the main element Pieces, SRAM_BASED the FPGA, the design began to verify the results, may experience many changes, this time as long as the JTAG s DOWNLOAD CABLE with the IMPACT software is conti<vkiy> 在 2025-06-08 上传 | 大小：776kb | 下载：0