资源列表
[VHDL编程] WaveGenerator-CPLD-10-05-09-16-28
说明:基于CPLD的DDS信号发生器,将I2Cflash中的波形数据读出,并将其并行输出,再通过DA转换,得到模拟波形。开发工具是quartusII7.2-The DDS signal generator based on CPLD will I2Cflash the waveform data read out, and its parallel output, and then through the DA converter, are analog waveform. Development t<朱澄澄> 在 2025-06-11 上传 | 大小:819kb | 下载:0
[VHDL编程] arm_move
说明:An effort has been made to design a robot, which loads and unloads an object to the station depending on the request. The sensor connected to the robot will sense the request and initiate the correct sequence of operation. The robot under design has<joja> 在 2025-06-11 上传 | 大小:26kb | 下载:0
[VHDL编程] jtd
说明:用VerilogHDL设计的交通灯控制器,经FPGA验证过-a process based on VerilogHDL is about traffic-light controlling.<tianqingse> 在 2025-06-11 上传 | 大小:15kb | 下载:0
[VHDL编程] vhdl
说明:该系统通过顶层模块,调用7底层模块实现。7大模块底层模块为:理想信源数据接收模块,理想信源数据缓存模块,LAPS成帧模块,加扰并发送LAPS帧模块,接收LAPS帧并解扰模块,接收LAPS帧数据缓存模块,解帧并发送数据给理想信源模块。另,还有一个fifo模块,以便两个缓存模块调用。-The system top-level module, called 7, the bottom module. Bottom-7 module module: the ideal source of data re<mao> 在 2025-06-11 上传 | 大小:6kb | 下载:0
[VHDL编程] ledcontrol
说明:FPGA驱动LED静态显示 --文件名:ledcontrol.vhd --功能:译码输出模块,LED为共阳接法 -FPGA-driven LED static display- File Name: ledcontrol.vhd- Function: decode the output module, LED is connected in a total of Yang<mao> 在 2025-06-11 上传 | 大小:1kb | 下载:0
[VHDL编程] NonPipelined_Design
说明:用VHDL实现的非流水线CPU设计,可以稍加改动变成流水线设计-VHDL implementation with non-pipelined CPU design<hewei> 在 2025-06-11 上传 | 大小:291kb | 下载:0