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[VHDL编程DualPortRam

说明:VHDL Dpram including clock divider, D4to7, Scan4Digit and of course TOP level as well as testbench info
<Brian> 在 2026-01-02 上传 | 大小:555kb | 下载:0

[VHDL编程Project_kw_2_until-LCD

说明:A code that i developed for temperature sensor using VHDL
<Brian> 在 2026-01-02 上传 | 大小:449kb | 下载:0

[VHDL编程RS232_kw_final

说明:A code to develop a communication link for RS232
<Brian> 在 2026-01-02 上传 | 大小:1.78mb | 下载:0

[VHDL编程Lab_intro2_ayjh

说明:A code to develop a cascade of counter
<Brian> 在 2026-01-02 上传 | 大小:475kb | 下载:0

[VHDL编程cricle

说明:点阵闪烁状态机,共10个状态,可调节闪烁频率-Dot flash state machine, a total of 10 states, adjustable flicker frequency
<夏江南> 在 2026-01-02 上传 | 大小:609kb | 下载:0

[VHDL编程mobile_sdram

说明:mobile DRAM Controller
<gooodman> 在 2026-01-02 上传 | 大小:4kb | 下载:0

[VHDL编程Video_ColorBar

说明:vhdl编写的程序,主要用来做彩条发生器,是CPLD开发的一个小例子而已,但是基础很重要嘛-vhdl programs written primarily used for color bar generator, is a small example of CPLD development only, but the basic thing is very important
<> 在 2026-01-02 上传 | 大小:514kb | 下载:0

[VHDL编程vhdl_codes

说明:this parallel to serial controller-this is parallel to serial controller
<Heramb> 在 2026-01-02 上传 | 大小:7kb | 下载:0

[VHDL编程a-vhdl-can-controller

说明:a vhdl can controller project using vhdl programmming language-a vhdl can controller project using vhdl programmming language..
<Rahul> 在 2026-01-02 上传 | 大小:110kb | 下载:0

[VHDL编程all-digital-fm-receiver

说明:all digital fm receiver using vhdl programming language project for electronics and communication engineering students.
<Rahul> 在 2026-01-02 上传 | 大小:1.47mb | 下载:0

[VHDL编程Design.Recipes.for.FPGAs.pdf

说明:Design Recipes for FPGAs (Peter Wilson) This book provides a rich toolbox of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, the book gives easy-to-find design techniques and templates
<ynona> 在 2026-01-02 上传 | 大小:1.36mb | 下载:0

[VHDL编程Writing-Testbenches-using-System-Verilog.tar

说明:Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from
<ynona> 在 2026-01-02 上传 | 大小:2.65mb | 下载:0
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