[VHDL编程] mole-game-rev1.0

说明：mole game to be implemented by verilog. LED # on corresponds to mole # to get up. LED # off corresponds to moe # to sit down. Game User press down button to turn off LED #. etc. Enjoy all. -mole game to be implemented by verilog. LED #
<> 在 2025-06-23 上传 | 大小：259kb | 下载：0

[VHDL编程] auto_toss_gawi_bawi_bo_sv-rev1.0

说明：Auto toss gawi bawi bo to be implemented by system verilog. This Game is simple game to be used by each hands between young people and old people. Winner is the final person.
<> 在 2025-06-23 上传 | 大小：182kb | 下载：0

[VHDL编程] digit_deletion_game-rev1.0

说明：digit deletion game to be implented by verilog. This game was used in casio game before 20 years. I made it in verilog. Game rule is simple. number is generated in random and user will delete number in display out of order. Have Fun.
<龍 龍 > 在 2025-06-23 上传 | 大小：129kb | 下载：0

[VHDL编程] parking_lot_rev1.0

说明：This Verilog source is to monitor the count of cars in 4 floors in parking lot. monitoring method is to use sensors to count Cars to enter into or leave out. Cars number is basic number enough small to learn algorithms.
<龍 龍 > 在 2025-06-23 上传 | 大小：85kb | 下载：0

[VHDL编程] led

说明：FPGA 键盘数码管、蜂鸣器的驱动程序,希望对大家有所帮组！-FPGA keyboard LED, buzzer driver, we want to help the group!
<123> 在 2025-06-23 上传 | 大小：2kb | 下载：0

[VHDL编程] VHDLreportoftrafficlight.wps.tar

说明：该代码通过时钟,状态循环控制及显示模块实现了对于两相邻十字路*通灯到控制,同时包含了对于两路*通灯延时启动,以及人行道情况的考虑-The code of the clock, cycle control and display module status achieved for the two adjacent intersections to control traffic lights,and includes traffic light intersection for the tw
<> 在 2025-06-23 上传 | 大小：731kb | 下载：0

[VHDL编程] VHDL

说明：计数器的VHDL程序，有运行图和运行结果-VHDL program counter, a diagram and the results
<青菜叶> 在 2025-06-23 上传 | 大小：380kb | 下载：0

[VHDL编程] seg_7

说明：Altera DE系列开发板都可以参考的基于Nios ii 的数码管控制显示0-f程序-display 0-f with 7-segment display on Altera DE series board.
<thomas yang> 在 2025-06-23 上传 | 大小：120kb | 下载：0

[VHDL编程] key

说明：基于Nios ii处理器的响应按键程序 -Processor-based Nios ii response key program
<thomas yang> 在 2025-06-23 上传 | 大小：106kb | 下载：0

[VHDL编程] test

说明：DE1开发板基于Nios ii的10秒钟语音录放程序-DE1 development board based on Nios ii 10 seconds voice recording program
<thomas yang> 在 2025-06-23 上传 | 大小：14kb | 下载：0

[VHDL编程] DE1_i2sound

说明：基于DE1的用verilog控制FPGA发声-The DE1-based sound with verilog control FPGA
<thomas yang> 在 2025-06-23 上传 | 大小：627kb | 下载：0

[VHDL编程] DE1_synthesizer

说明：基于DE1开发板的verilog 响应键盘发声的声音合成器-DE1 development board based on the response to the voice synthesizer keyboard sound
<thomas yang> 在 2025-06-23 上传 | 大小：3.71mb | 下载：0