资源列表
[VHDL编程] p_in_s_out
说明：并入串出寄存器设计 datain[7..0] 是八位数据输入端，并行输入； clk 脉冲输入端，数据的移位靠该引脚触发； load 是读入数据控制端； dataout 一位数据的输出端。 -String into a register Design datain [7 .. 0] is the eight-bit data input terminal, parallel inpu<吴胜兵> 在 2025-12-25 上传 | 大小：305kb | 下载：0
[VHDL编程] digital-colok
说明：用quartusII编写的vhdl代码，在板子上输出的显示就是数字钟，也可以重置、设置时间。-With written in VHDL quartusII code, the output is the digital clock is displayed on the board, you can also reset, and the time.<> 在 2025-12-25 上传 | 大小：9.87mb | 下载：0
[VHDL编程] Pld-based-VGA-display
说明：基于pld和Verilog语言的VGA显示，内容为雨后彩虹。-Pld-based VGA display<郑惠文> 在 2025-12-25 上传 | 大小：881kb | 下载：0
[VHDL编程] Experiment
说明：可编程逻辑器件VHDL实现的3线-8线译码器-VHDL 3-8 priority encoder decoder<alex> 在 2025-12-25 上传 | 大小：54kb | 下载：0
[VHDL编程] 4-bit-Multiplier
说明：IT is a 4 bit multiplier vhdl coding file which is run in altera quatrs - II. in which 4 binary bit is multiplied and waveform can be obtained<Henal patel> 在 2025-12-25 上传 | 大小：46kb | 下载：0
[VHDL编程] 4-bit-ALU
说明：it is a 4 bit airthmatic logic unit in which all basic mathematical operation of binary number can done. it is a vhdl code file<Henal patel> 在 2025-12-25 上传 | 大小：270kb | 下载：0
[VHDL编程] 4-bit-Ripple-Carry-adder
说明：it is 4 bit ripple carry adder. it is one type of counter you can say. in which carry is added. it is vhdl code and its waveform which is run in altera quars II.<Henal patel> 在 2025-12-25 上传 | 大小：25kb | 下载：0
[VHDL编程] Melay_1001
说明：it is Mealy model s vhdl code. and it was implemented and run in Altera quarts - -it is Mealy model s vhdl code. and it was implemented and run in Altera quarts - II<Henal patel> 在 2025-12-25 上传 | 大小：24kb | 下载：0
[VHDL编程] Moore_1001
说明：it is a moorey model s vhdl code which was implemented and run in altera Quarts - II<Henal patel> 在 2025-12-25 上传 | 大小：21kb | 下载：0
[VHDL编程] Frequency_Div
说明：it is vhdl code for "frequency divider" which was implemented and run in altera quarts- -it is vhdl code for "frequency divider" which was implemented and run in altera quarts- II<Henal patel> 在 2025-12-25 上传 | 大小：24kb | 下载：0