资源列表
[VHDL编程] IO-timing-constrain-in-fpga
说明：对FPGA的IO口的时序分析小结，能够详细理解其约束时序规则-FPGA timing analysis summary of IO port, capable of a detailed understanding of its timing constraint rules<张龙> 在 2025-06-19 上传 | 大小：185kb | 下载：0
[VHDL编程] IIC
说明：硬件语言verilog实现IIC控制器，严格按照IIC协议编写硬件控制器行为及代码-Hardware language verilog realize IIC controllers, written in strict accordance with IIC protocol hardware controller behavior and codeHardware language verilog realize IIC controllers, written in strict acco<张龙> 在 2025-06-19 上传 | 大小：2kb | 下载：0
[VHDL编程] MVLSI_CBP_16.-FPGA-based-for-Implementation-of-Mu
说明：Paper on FPGA-based-for-Implementation-of-Multi-Serials-to-Ethernet-Gateway<PADDU> 在 2025-06-19 上传 | 大小：353kb | 下载：0
[VHDL编程] divby4.5.v
说明：This Divider by 4.5.-This is Divider by 4.5.<Gourav Agarwal> 在 2025-06-19 上传 | 大小：1kb | 下载：0
[VHDL编程] lfsrupdwn.v
说明：This left shift register.-This is left shift register.<Gourav Agarwal> 在 2025-06-19 上传 | 大小：1kb | 下载：0
[VHDL编程] divby3.v
说明：This Divider by 3.-This is Divider by 3.<Gourav Agarwal> 在 2025-06-19 上传 | 大小：1kb | 下载：0
[VHDL编程] jkff_behav.v
说明：This is JK-FF in Behavioural Style.<Gourav Agarwal> 在 2025-06-19 上传 | 大小：1kb | 下载：0
[VHDL编程] FX2LP-FPGA
说明：xilinx FPGA XC6LX9 与CY7C68013通信程序-xilinx FPGA XC6LX9 and communication program CY7C68013<书才> 在 2025-06-19 上传 | 大小：587kb | 下载：0
[VHDL编程] verilog_sdram
说明：I used code verilog. Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to<thuanbk> 在 2025-06-19 上传 | 大小：28kb | 下载：0
[VHDL编程] hash_function_sha3
说明：The synthesis software is Xilinx ISE version 14.4. The low throughput core has been synthesized targeting a very cheap Spartan 3 (XC3S5000-4FG900). This project is licensed under the Apache License, version 2. I prefered on the internet<thuanbk> 在 2025-06-19 上传 | 大小：6kb | 下载：0