资源列表
[VHDL编程] d-Flip-Flop
说明:D flip flop and some other codes added together recomended use is adding layer not use in a single bench<Dou> 在 2025-06-22 上传 | 大小:2kb | 下载:0
[VHDL编程] mux8to1_with_if
说明:this code to input 8 different data and make them out sequentialy -this code to input 8 different data and make them out sequentialy<freaker> 在 2025-06-22 上传 | 大小:18kb | 下载:0
[VHDL编程] UVM_Guidlines
说明:UVM Coding Guidelines for verification<tguy99999> 在 2025-06-22 上传 | 大小:63kb | 下载:0
[VHDL编程] ahb_master
说明:AHB master system generator in verilog<Prashanth R> 在 2025-06-22 上传 | 大小:9kb | 下载:0
[VHDL编程] Array-multiplier
说明:Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs<Prashanth R> 在 2025-06-22 上传 | 大小:1kb | 下载:0
[VHDL编程] pid
说明:pid controller design based vhdl code in xilinx code-pid controller design based vhdl code in xilinx code.....................<GOPALAKRISHNAN E> 在 2025-06-22 上传 | 大小:1kb | 下载:0
[VHDL编程] piano_fina1
说明:基于VHDL的简易电子琴游戏,可实现发声,点阵显示,倒数计时,计分等功能-VHDL simple electronic organ based games, can realize the voice, dot matrix display, countdown, scoring function<zhangxiangrui> 在 2025-06-22 上传 | 大小:1011kb | 下载:0
[VHDL编程] router_five_port
说明:On-chip routers typically have buffers dedicated to their input or output ports for temporarily storing packets in case contention occurs on output physical channels. Buffers, unfortunately, consume significant portions of router area and pow<Rosario Gowthaman> 在 2025-06-22 上传 | 大小:5kb | 下载:0