资源列表
[VHDL编程] UART_FPGA
说明:此vhdl程序实现了在FPGA上构建UART通信串口。分为两部分,UART的发送端transfer和接收端receiver。需要外部根据需求提供波特率时钟。-This program implements the building vhdl UART serial interface on the FPGA. Divided into two parts, UART transfer sender and receiver receiver. Required to provide the ba<lmy> 在 2025-06-22 上传 | 大小:4kb | 下载:0
[VHDL编程] LSP
说明:THIS CODE IS FOR COMPUTING LSP USING HARDWARE REALIZATION IN TERMS OF MUX AND FF.<kirubadoni> 在 2025-06-22 上传 | 大小:11kb | 下载:0
[VHDL编程] LSP-NEW
说明:THIS FOR UPDATING CODE FOR LSP.-THIS IS FOR UPDATING CODE FOR LSP.<kirubadoni> 在 2025-06-22 上传 | 大小:9kb | 下载:0
[VHDL编程] BARREL-NEW
说明:THIS USED TO STORE VALUES i.e barrel-THIS IS USED TO STORE VALUES i.e barrel<kirubadoni> 在 2025-06-22 上传 | 大小:8kb | 下载:0
[VHDL编程] PISO-NEW
说明:THIS FOR STORING PURPOSE. THE INPUT IS IN PARALLEL AND OUTPUT IS IN SERIAL.-THIS IS FOR STORING PURPOSE. THE INPUT IS IN PARALLEL AND OUTPUT IS IN SERIAL.<kirubadoni> 在 2025-06-22 上传 | 大小:9kb | 下载:0
[VHDL编程] binary
说明:this is for low power dsp for wireless nodes (binary tree computation)<kirubadoni> 在 2025-06-22 上传 | 大小:2kb | 下载:0
[VHDL编程] scaling
说明:A camera raw image file contains minimally processed data the image sensor of either a digital camera, image scanner, or motion picture film scanner. Raw files are named so because they are not yet processed and therefore are not ready to be printed<Prabhu> 在 2025-06-22 上传 | 大小:6kb | 下载:0
[VHDL编程] 3Digit_7segment_ind_decoder
说明:3 Digit BCD to 7 segment indicator decoder<Sergey> 在 2025-06-22 上传 | 大小:1kb | 下载:0
[VHDL编程] ADC_AD7366_poll
说明:Module for AD7366 ADC po-Module for AD7366 ADC poll<Sergey> 在 2025-06-22 上传 | 大小:2kb | 下载:0
[VHDL编程] ADS7835_2x4
说明:Module for 2 AD7835 ADC po-Module for 2 AD7835 ADC poll<Sergey> 在 2025-06-22 上传 | 大小:1kb | 下载:0