[VHDL编程] rs_232

说明：Comunication rs232 in vhdl
<Thiago Amaral> 在 2025-06-27 上传 | 大小：1kb | 下载：0

[VHDL编程] equalizer

说明：This the code for the channel equalizer and the test bench for this in the verilog code.-This is the code for the channel equalizer and the test bench for this in the verilog code.
<rion> 在 2025-06-27 上传 | 大小：1kb | 下载：0

[VHDL编程] convolution

说明：This the code for the convolutional and the test bench for this in the verilog code.-This is the code for the convolutional and the test bench for this in the verilog code.
<rion> 在 2025-06-27 上传 | 大小：1kb | 下载：0

[VHDL编程] demapperSharp1(16QAM)

说明：This the code for the demapper in the verilog code.-This is the code for the demapper in the verilog code.
<rion> 在 2025-06-27 上传 | 大小：1kb | 下载：0

[VHDL编程] inter_deleaver

说明：This the code for the interleaver and the deinterleaver in the verilog code.-This is the code for the interleaver and the deinterleaver in the verilog code.
<rion> 在 2025-06-27 上传 | 大小：2kb | 下载：0

[VHDL编程] mapperSharp1(16QAM)

说明：This the code for the mapper in the verilog code.-This is the code for the mapper in the verilog code.
<rion> 在 2025-06-27 上传 | 大小：1kb | 下载：0

[VHDL编程] mt9d112_ddr2

说明：镁光MT9基于FPGA图像采集模块，该模块可同时采集两路视频信号。其包括完整的时序和接口、ddr2内存数据写入和存储、qsys系统的搭建、FPGA与NIOS II联合设计-Micron MT9 based on FPGA image acquisition module, the module can simultaneously capture two video signals. Including the complete timing and interface, ddr2 memory
<豪> 在 2025-06-27 上传 | 大小：37.39mb | 下载：0

[VHDL编程] HDMI_4AV

说明：该源码为基于FPGA的HDMI显示的一拖四的AV视频采集。该模块可方便移植在需要使用HDMI高清显示的场合，并且可将VGA显示一分为四，方便各个窗口显示不同的图像信息-The source for the FPGA-based HDMI display of a four of the AV video capture. The module can be easily transplanted in the need to use the HDMI high-definition displa
<豪> 在 2025-06-27 上传 | 大小：1.94mb | 下载：0

[VHDL编程] HDMI_FPGA

说明：该源码可基于FPGA设置多分辨率的HDMI显示，且其包含了完整的时序和端口、地址映射，可以很方便的将其移植-The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted
<豪> 在 2025-06-27 上传 | 大小：5.71mb | 下载：0

[VHDL编程] RD1213_Video_Pipeline

说明：This document describes the structure and implementation of a video pipeline demo design running in the Lattice ECP3-150EA-8FN1156C device based on the Sparrowhawk FX Board. This demo takes two of the four video streams DVI and SDI inputs and the
<吴> 在 2025-06-27 上传 | 大小：6.44mb | 下载：0

[VHDL编程] FIFOonFPGAtoUSB

说明：这个一个基于FPGA的FIFO的传输资料，可以用在USB的传输上，里面有视频有源代码，还有估计的设计，相关的文档说明等等。-The transmission of a data FIFO of FPGA-based, can be used on USB transmission, which has a video source code, as well as estimates of design, related documentation, and so on.
<jav> 在 2025-06-27 上传 | 大小：12.07mb | 下载：0

[VHDL编程] fft4_T

说明：4点FFT处理器设计，流水线式结构。采用状态机，不停地循环。-4-point FFT processor design, pipelined structure. Using the state machine, keep the cycle.
<王岩> 在 2025-06-27 上传 | 大小：775kb | 下载：0