资源列表
[VHDL编程] RS232
说明:基于quartusii的用verilog编写的rs232串口程序(QuartusII based on Verilog prepared by the RS232 serial procedures)<qiaodecheng > 在 2025-06-09 上传 | 大小:926kb | 下载:0
[VHDL编程] VERILOG_HDl
说明:verilog 初学者常用模块,可作为初学者实验使用(Verilog beginners commonly used modules, can be used as beginners experimental use)<大老鼠 > 在 2025-06-09 上传 | 大小:103kb | 下载:0
[VHDL编程] color_converter_latest.tar
说明:彩色空间转换的VHDL源代码,可以实现CIE XYZ<->RGB, different RGB<->RGB和RGB<->YCbCr之间的相互转换,使用3x3矩阵模板(a color transform tasks such as CIE XYZ<->RGB, different RGB<->RGB and RGB<->YCbCr operations. The main part of color conversions f<athbest > 在 2025-06-09 上传 | 大小:328kb | 下载:0
[VHDL编程] Z-turn-examples-master
说明:# Z-turn-examples The repository with my simple Z-turn examples, to be used as templates for more serious projects. Please note, that the Buildroot configuration in my designs sets the root password to "test". Setting the password is n<forestmeng > 在 2025-06-09 上传 | 大小:2.57mb | 下载:0
[VHDL编程] axi_ipif_v2.3
说明:The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point<forestmeng > 在 2025-06-09 上传 | 大小:394kb | 下载:0