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[VHDL编程vwgif

说明:Based on negative entropy largest independent component analysis, You can achieve data classification and regression pattern recognition, Partially achieved tracking speed iterative relaxation algorithm.
<meigengping > 在 2025-12-27 上传 | 大小:10kb | 下载:0

[VHDL编程mpjcy

说明:Including regression analysis and probability and statistics, Modern signal processing jobs when the graduate, Matlab for beginner students will help.
<meigengping > 在 2025-12-27 上传 | 大小:10kb | 下载:0

[VHDL编程qd317

说明:Weighted acceleration, In the MATLAB image texture feature, Achieve serial data acquisition.
<meigengping > 在 2025-12-27 上传 | 大小:10kb | 下载:0

[VHDL编程hiisi

说明:Codec ldpc code implementation Mainly based on the mtlab procedures, Relief computing classification weight.
<meigengping > 在 2025-12-27 上传 | 大小:10kb | 下载:0

[VHDL编程hwcat

说明:Simulation of the effect is very good, Since writing the curvature calculation function, Matlab for beginner students will help.
<senkunmaohui > 在 2025-12-27 上传 | 大小:10kb | 下载:0

[VHDL编程yaiyuifeng

说明:Using matlab to calculate the Mahalanobis distance for the image, SNR largest independent component analysis algorithm, Matlab to achieve user-friendly.
<pouliutangsai > 在 2025-12-27 上传 | 大小:10kb | 下载:0

[VHDL编程jkiuk

说明:Graduation useful Fractal dimension calculation algorithm matlab code blankets, Linear array using cut than learning laid upon the right control of the main sidelobe ratio.
<pouliutangsai > 在 2025-12-27 上传 | 大小:10kb | 下载:0

[VHDL编程banqang_v19

说明:Genetic algorithms using MATLAB path planning, Thermonuclear using weighting factors Energy spectrum analysis and calculation.
<nenkingnaogen > 在 2025-12-27 上传 | 大小:10kb | 下载:0

[VHDL编程bayer_3RGB_interpolation

说明:bayer转rgb 源代码,Verilog语言,FPGA上使用,(Bayer to RGB source code, Verilog language, FPGA use,)
<hezhnew > 在 2025-12-27 上传 | 大小:10kb | 下载:0

[VHDL编程ASKMod

说明:能够实现一种ASK的调制方法,语言为verilog(Can achieve a modulation method of ASK, the language is Verilog)
<亚东 > 在 2025-12-27 上传 | 大小:10kb | 下载:0

[VHDL编程counter

说明:Counter example for FPGA with VHDL
<arza > 在 2025-12-27 上传 | 大小:10kb | 下载:0

[VHDL编程fifo

说明:fifo in qurtuas using verilog
<taewoo > 在 2025-12-27 上传 | 大小:10kb | 下载:0
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