资源列表
[VHDL编程] qpsk_mod
说明:QPSK modulation using vhdl programming ..i hope it ll be useful-QPSK modulation using vhdl programming ..i hope it ll be useful...<she-sheetal> 在 2025-06-17 上传 | 大小:9kb | 下载:0
[VHDL编程] ahb_master
说明:AHB master system generator in verilog<Prashanth R> 在 2025-06-17 上传 | 大小:9kb | 下载:0
[VHDL编程] LSP-NEW
说明:THIS FOR UPDATING CODE FOR LSP.-THIS IS FOR UPDATING CODE FOR LSP.<kirubadoni> 在 2025-06-17 上传 | 大小:9kb | 下载:0
[VHDL编程] PISO-NEW
说明:THIS FOR STORING PURPOSE. THE INPUT IS IN PARALLEL AND OUTPUT IS IN SERIAL.-THIS IS FOR STORING PURPOSE. THE INPUT IS IN PARALLEL AND OUTPUT IS IN SERIAL.<kirubadoni> 在 2025-06-17 上传 | 大小:9kb | 下载:0
[VHDL编程] sales
说明:自动售货机,与现实生活中的售货机功能类似,可以自动进行找零-Vending machines, vending machines and similar real life, there is a function to automatically calculate the price of goods<white snow> 在 2025-06-17 上传 | 大小:9kb | 下载:0
[VHDL编程] hdbn
说明:This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-T G.703. Note: HDB2 and<fronders> 在 2025-06-17 上传 | 大小:9kb | 下载:0
[VHDL编程] Interleaver_Deinterleaver
说明:通信中卷积交织/解交织FPGA源程序,采用verilogHDL代码实现,包含测试程序,经过验证。-Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.<ranbowang> 在 2025-06-17 上传 | 大小:9kb | 下载:0