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[VHDL编程] queue
说明:完成FIFO功能:the first element added to a queue will occur in the first place in the queue, the second element added to the queue will be after the first one-a kind of First-In-First-Out (FIFO) data structure,the first element added to a queue will occ<董俊翔> 在 2025-06-08 上传 | 大小:546kb | 下载:0
[VHDL编程] FaceDetection
说明:基于adoost的fpga人脸检测程序,代码采用了verilog编写,用的是xilinx的virtex5芯片-face detection based on adboost. verilog is used,and virtex5 it isimplementated on virtex5.<张驠> 在 2025-06-08 上传 | 大小:7.93mb | 下载:0
[VHDL编程] DDS-VERILOG
说明:DDS的信号发生器verilog代码 可直接用于编程 已经测试-Verilog code of the DDS signal generator which can be used directly in the programming has been tested<佘琪> 在 2025-06-08 上传 | 大小:3kb | 下载:0